Siglent oscilloscope - unexpected frequencies

[einfachprima]

Let me summarize what I learned so far:

• One (cheap) ADC is not fast enough for 1 GSa/s. So there are ten ADCs (interleaved, 1ns shift).
• This explains the 100 MHz signal. There is also the crystal oscillator on the PCB, I think it triggers the ADC array.
• The raw sampling rate is always 1GSa/s, for lower rates samples are discarded.
• The gain of each ADC has to match. This seems to be the problem with my scope.
• The factory calibration is done during production. It was either not good enough or there was a drift over the years or maybe an incomplete firmware/cfg update.
• Maybe calibration can be repeated, but this requires additional equipment and additional software.
• I don't know how the calibration data is stored in the scope. I can't find it in the list of serial commands. Maybe by a JTAG interface. I doubt there is a documentation available.

[tautech]

Cal procedures will be similar to those in later C*L models and it's closed box while connected to a calibrator and a PC running the Cal routine.
Outlined on P26 here:
http://siglentna.com/wp-content/uploads/dlm_uploads/2017/10/SDS1000CNL_ServiceManual_en.pdf

Before considering going down this road do the PSU checks on P46......not that it's likely to be the issue but something that should be excluded from investigations.

[einfachprima]

The amplitude of the 100 MHz spurs is not normal.

I'm wondering how many dB the spur amplitude is actually down from CW amplitude. The FFT is obviously zoomed-in, so I can't see the 5MHz amplitude. The sine wave already looks pretty jittery in the time domain, though, and I guess it's not just random noise...

If the capture buffer can be saved, then one could de-interleave the samples into N sequences (where N is the number of interleaved ADCs), FFT-analyze the samples from each ADC separately (in order to rule out other oddities - other than interleaving spurs), and also calculate e.g. gain/offset correction for each ADC. Correction parameters only help for offline analysis of captured data, though, if they cannot be fed back into the scope 

I'm also wondering whether there are unexpected spurs at other frequencies, too, in the whole range from 0...fs/2?

And I'd also test with a few signal frequencies which are not integral fractions of the sampling rate (for some considerations this makes a significant difference - although I guess not in this particular case).

Here is the full spectrum with a 4.5 MHz sine (FFT in dBVrms):


No signal, with V bias:


With Long Mem (signal in time domain is better visible):

[thinkfat]

I could identify the following items:

• crystal oscillator 100.00 MHz
• HA04 27K A8FL: ?
• HImax HX8817ALAG: TCON (Timing Controller Unit)
• CY7C1386D: SRAM
• Altera Cyclone IV: FPGA
• Altera MAX V: CPLD
• 3x IC without imprint

Who knows how these chips work together?

I'd say the "HA04" is a PLL. The passives above the IC are the load caps for the crystal, one resistor across the oscillator inputs, one resistor to limit the current. The passives just below the crystal could be the loop filter.

[gf]

Is this service adjustment done mechanically (potentiometer on the PCB,...) or by a software adjustment with a special proprietary tool?

The adjustment can be easily applied by post-processing the samples in the digital domain, so likely no analog circuitry is involved.

It should be easy for the self-calibration procedure to determine the necessary gain and offset values for aligning the ADCs, so in fact I would be rather surprised if this would require a factory calibration (but who knows )

I take it for granted that you did not forget to run self-calibration, did you?

Here is the full spectrum with a 4.5 MHz sine (FFT in dBVrms):

So you're facing a SFDR of about 34dB, or maybe a little bit more, since the sine wave amplitude was not full-scale yet.
The handbook specifes SFDR >=40dB (but it does not promise significantly more either).

[ Just for comparison the typical SFDR including inverleaving spurs for the HMCAD1511 (which is used in the SDS1000X-E models and also in some other DSOs in this class): 44dBc in dual Ch Mode @500MsPs, 49dBc in single Ch Mode @1000MsPs, and 57dB in quad Ch Mode @250MsPs. ]

[einfachprima]

It should be easy for the self-calibration procedure to determine the necessary gain and offset values for aligning the ADCs, so in fact I would be rather surprised if this would require a factory calibration (but who knows )

I take it for granted that you did not forget to run self-calibration, did you?

I've started the self calibration, but this didn't solve the problem.

[einfachprima]

3x IC without imprint

Those are the memory chips and over the years many CN and CNL models have been upgraded to the CM/CML mem spec with the addition of these chips.
A hunt through the forum should find threads/posts about these upgrades and what Pt# these IC's actually are.

I don't think those are memory chips. Meanwhile I've found two additional chips on the back side of the PCB. I think those are ADCs, 5x dual ADCs, probably AD9288 or similar. I don't know why Siglent has removed the imprint, maybe they are overclocked.

[einfachprima]

Before considering going down this road do the PSU checks on P46......not that it's likely to be the issue but something that should be excluded from investigations.

Today I've checked the voltages of the psu, they are all within the specification.

I think there is nothing more I can do, a factory calibration requires a Fluke generator and a special calibration software.

So I will keep my DSO and use one of the workarounds if needed. Maybe I'll add a new DSO to my wishlist 

Thanks for the discussion and all the hints