Siglent oscilloscope - unexpected frequencies

[einfachprima]

After using an analogue oscilloscope during the last 20 years, I got an older, rarely used DSO from a friend one week ago:
Siglent SDS1102CM, Software 5.02.02.13, Hardware 11-62-3.3. This model is no longer supported and is no longer mentioned on the Siglent website.

It works fine and has all features I currently need. But I experienced unexpected frequencies during my measurements.
Here is a 5 MHz sine signal from a frequency generator (FY6900):



There you can see additional frequencies added to the 5 MHz signal. The FFT shows me three frequencies: 95 MHz, 100 MHz, 105 MHz.

To narrow down the problem I removed the frequency generator and checked the "noise":



This looks good as long as the level is near 0 V. But if I add a DC voltage or if I shift the voltage bias I get this result:



That's the problem. There is a strange 100 MHz signal.

I performed some additional checks:

• I started a self calibration. No difference.
• I used the scope outside the house to avoid electromagnetic disturbance. No difference.
• The coupling (DC/AC) has no influence.
• The amplitude is independent of the input amplifier. For all values (2mV/DIV ... 10V/DIV) I get a similar screen.
• The BW limiter (20 MHz) has no influence. So the 100 MHz signal comes from the oscilloscope itself.
• On channel two the amplitude of the 100 MHz signal is a bit lower but still present.

So I expect there is a kind of "crosstalk" from the PLL or a similar circuit to the input of the ADC. Or a problem with the ADC.

Meanwhile I found three different workarounds:

• Using the average function (for periodic signals)
• Switching from Realtime to Equivalent Time if faster than 100ns/DIV (for periodic signals)
• Activating the digital notch filter at +/- 100 MHz (unfortunately the frequency limits are automatically changed if I switch the time base)

Is this a common problem on older DSOs? Can it be fixed?

[tautech]

Wow, an old 5" display CM, they are getting on now, ~2010 vintage.

Yes it might be possible that spur is from the internal clock but now you know about it you can work around it like one does with spurious peaks in spectrum analysers where the limits for them are specified in datasheets. I've not seen a spur specification listed for FFT in cheap DSO's.

Generally we get a better FFT with many more periods/cycles of the waveform on the display at a much slower timebase setting. Also we can see this spur more at maximum sensitivity were in these old models this is a magnification of real sensitivity and down in the region where a spectrum analyser would be a better tool for the job.

Still it's an interesting observation that some here might also like to investigate the lower limits of FFT to see if similar spurs might appear.

[David Hess]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

[Kleinstein]

With these cheap Chinese generators there is also a small chance that the extra frequencies are actually there.
However some gain / offset mismatch with interleaved ADCs looks very plausible.

[thinkfat]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

Though the sampling clock is 500MS/s...

[David Hess]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

Though the sampling clock is 500MS/s...

It might be but it is divided by the number of interleaved ADCs although 5 would be an odd number; 4 or 8 is typical.

[einfachprima]

Wow, an old 5" display CM, they are getting on now, ~2010 vintage.

OT:
My analogue oscilloscope (Oscillarzet M 222) from 1967 is vintage. But it still works.

At the moment it is not necessary to throw away the DSO from 2011. 100 MHz, 1Gs/s, 2M memory is ok.
The newer models (SDS1104X-E, ...) have some nice features (screen resolution, false colors, 4 channels, serial decoder, Bode plot, LAN/Wifi, fastrr FFT with better resolution, ...) but currently all of my measurements can also be done with the 1102CM.  Maybe in the future I will switch to a modern DSO.

BTW I have no problems with the FFT. I needed some hours to understand how the UI works and how the time base and memory depth affect the FFT frequency limits. It was interesting to see the three frequencies (100 MHz & 100 MHz +/- 5MHz. I can also zoom out to see the full spectrum with the strong peak at 5 Mhz.

[einfachprima]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

Though the sampling clock is 500MS/s...

It might be but it is divided by the number of interleaved ADCs although 5 would be an odd number; 4 or 8 is typical.

The peak is independent from the sampling rate. 1GS/s, 500 MS/s or 250 MS/s: The frequency is always 100 Mhz.

[einfachprima]

Older DSOs have service adjustments for this while newer instruments should do it automatically.

Is this service adjustment done mechanically (potentiometer on the PCB,...) or by a software adjustment with a special proprietary tool?

[ogden]

I say that scope is faulty. It is highly unlikely that such amount of leakage could be considered as acceptable by manufacturer. Something happened to that thing over time.

[David Hess]

It might be but it is divided by the number of interleaved ADCs although 5 would be an odd number; 4 or 8 is typical.

The peak is independent from the sampling rate. 1GS/s, 500 MS/s or 250 MS/s: The frequency is always 100 Mhz.

The true sampling rate is constant.  The reported sampling rate is the decimated rate after samples are discarded.  For technical reasons the digitizer always operates at the fastest sampling rate.

You might try seeing if the tone is different when both channels are active.

[einfachprima]

You might try seeing if the tone is different when both channels are active.

If I activate the second channel the max. sampling rate is 500 MS/s (as expected) but the peak is unchanged (100 MHz).

[thinkfat]

It might be but it is divided by the number of interleaved ADCs although 5 would be an odd number; 4 or 8 is typical.

The peak is independent from the sampling rate. 1GS/s, 500 MS/s or 250 MS/s: The frequency is always 100 Mhz.

The true sampling rate is constant.  The reported sampling rate is the decimated rate after samples are discarded.  For technical reasons the digitizer always operates at the fastest sampling rate.

You might try seeing if the tone is different when both channels are active.

If the true sample rate is always 1GSa/s, then with 10 interleaved ADCs you'd have you 100MHz.

[ogden]

If the true sample rate is always 1GSa/s, then with 10 interleaved ADCs you'd have you 100MHz.

Thing is that ADC of this scope (HMCAD1511) internally have 4 interleaved ADC's
[edit] As I am corrected later, this ^^ was not true, there is no HMCAD1511 in this scope

[rf-loop]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

^ This. (gain and offset)
Also there is more or less clock timing errors between 10 ADC's. (if I remember right there is 5x dual DAC.
(this discuss about timing these ADC's is also somewhere in old Hantek thread - roughly same kind of construction.)

But old SDS CM is still live... it is still more than no scope at all

[rf-loop]

My guess is that the sampling clock is leaking through the interleaved digitizer because the gain is not matched between sections.  Older DSOs have service adjustments for this while newer instruments should do it automatically.

Though the sampling clock is 500MS/s...

It might be but it is divided by the number of interleaved ADCs although 5 would be an odd number; 4 or 8 is typical.

The peak is independent from the sampling rate. 1GS/s, 500 MS/s or 250 MS/s: The frequency is always 100 Mhz.

Interleaved ADC's  clock is  fixed 100MHz independent of sampling rate displayed. Sampling rate is, with 1 channel in use, 1GSa/s (10ADC) and if 2 channel in use 500MSa/s both (5+5ADC).  Other displayed current samplerates are after ADC decimated samplerates.

[rf-loop]

If the true sample rate is always 1GSa/s, then with 10 interleaved ADCs you'd have you 100MHz.

Thing is that ADC of this scope (HMCAD1511) internally have 4 interleaved ADC's

This is some kind of alternative trumpth. (=bullshit)

This OP's scope is old SDS1102CM !

There is not HMCAD1511 inside.

[ogden]

This is some kind of alternative trumpth. (=bullshit)
This OP's scope is old SDS1102CM !
There is not HMCAD1511 inside.

No need to be so toxic. Yes you are right, I got wrong model number, there is no HMCAD1511 inside. Satisfied?

[BobRyan]

I have a similar vintage siglent-made scope (BK 2557 / sds1204cfl) and I'm unable to reproduce this. Only tested with 50ohm input impedance.

EDIT: added siglent model

[Kleinstein]

I have a similar vintage siglent-made scope (BK 2557 / sds1204cfl) and I'm unable to reproduce this. Only tested with 50ohm input impedance.

EDIT: added siglent model

The amplitude of the 100 MHz spurs is not normal. There is likely some internal adjustment off to produce so much of the unwanted signal. A well working scope may still have a tiny rest, but not that amplitude.

The main point is, if there is an easy fix (e.g. adjustment of some internal trimmers or even a special internal cal procedure to call). So it is really good question, with some hope that someone has suitable instructions for a fix or a service manual.

[tautech]

I have a similar vintage siglent-made scope (BK 2557 / sds1204cfl) and I'm unable to reproduce this. Only tested with 50ohm input impedance.

EDIT: added siglent model

CFL models are 2GSa/s whereas CN, CM and later L and Plus models are all 1GSa/s so not the perfect comparison. 
I had a play with a SDS1102CML+ yesterday but couldn’t find any spurs however I need to do more to properly  replicate the OP’s settings........maybe later today when other jobs are done.

[gf]

Thing is that ADC of this scope (HMCAD1511) internally have 4 interleaved ADC's

OT: Just by the way, HMCAD1511 has 4 multiplexable analog inputs, but even 8 ADC branches (which can be fine-gain adjusted separately). I.e 4CH mode @250MSPS is 2x interlaved, too.

[gf]

The amplitude of the 100 MHz spurs is not normal.

I'm wondering how many dB the spur amplitude is actually down from CW amplitude. The FFT is obviously zoomed-in, so I can't see the 5MHz amplitude. The sine wave already looks pretty jittery in the time domain, though, and I guess it's not just random noise...

If the capture buffer can be saved, then one could de-interleave the samples into N sequences (where N is the number of interleaved ADCs), FFT-analyze the samples from each ADC separately (in order to rule out other oddities - other than interleaving spurs), and also calculate e.g. gain/offset correction for each ADC. Correction parameters only help for offline analysis of captured data, though, if they cannot be fed back into the scope 

I'm also wondering whether there are unexpected spurs at other frequencies, too, in the whole range from 0...fs/2?

And I'd also test with a few signal frequencies which are not integral fractions of the sampling rate (for some considerations this makes a significant difference - although I guess not in this particular case).

[einfachprima]

I took two picture of the PCB, maybe this helps:





I could identify the following items:

• crystal oscillator 100.00 MHz
• HA04 27K A8FL: ?
• HImax HX8817ALAG: TCON (Timing Controller Unit)
• CY7C1386D: SRAM
• Altera Cyclone IV: FPGA
• Altera MAX V: CPLD
• 3x IC without imprint

Who knows how these chips work together?

[tautech]

The sine wave already looks pretty jittery in the time domain, though, and I guess it's not just random noise...

These old CM models had a low res display, just 400 x 240 IIRC, maybe even less as they were 5" and they IME were never known for high fidelity viewing. Also when using Stop mode only the last buffer capture get pushed to the display instead of in Run mode where the display is updated at some 30/s.

3x IC without imprint

Those are the memory chips and over the years many CN and CNL models have been upgraded to the CM/CML mem spec with the addition of these chips.
A hunt through the forum should find threads/posts about these upgrades and what Pt# these IC's actually are.

[einfachprima]

Let me summarize what I learned so far:

• One (cheap) ADC is not fast enough for 1 GSa/s. So there are ten ADCs (interleaved, 1ns shift).
• This explains the 100 MHz signal. There is also the crystal oscillator on the PCB, I think it triggers the ADC array.
• The raw sampling rate is always 1GSa/s, for lower rates samples are discarded.
• The gain of each ADC has to match. This seems to be the problem with my scope.
• The factory calibration is done during production. It was either not good enough or there was a drift over the years or maybe an incomplete firmware/cfg update.
• Maybe calibration can be repeated, but this requires additional equipment and additional software.
• I don't know how the calibration data is stored in the scope. I can't find it in the list of serial commands. Maybe by a JTAG interface. I doubt there is a documentation available.

[tautech]

Cal procedures will be similar to those in later C*L models and it's closed box while connected to a calibrator and a PC running the Cal routine.
Outlined on P26 here:
http://siglentna.com/wp-content/uploads/dlm_uploads/2017/10/SDS1000CNL_ServiceManual_en.pdf

Before considering going down this road do the PSU checks on P46......not that it's likely to be the issue but something that should be excluded from investigations.

[einfachprima]

The amplitude of the 100 MHz spurs is not normal.

I'm wondering how many dB the spur amplitude is actually down from CW amplitude. The FFT is obviously zoomed-in, so I can't see the 5MHz amplitude. The sine wave already looks pretty jittery in the time domain, though, and I guess it's not just random noise...

If the capture buffer can be saved, then one could de-interleave the samples into N sequences (where N is the number of interleaved ADCs), FFT-analyze the samples from each ADC separately (in order to rule out other oddities - other than interleaving spurs), and also calculate e.g. gain/offset correction for each ADC. Correction parameters only help for offline analysis of captured data, though, if they cannot be fed back into the scope 

I'm also wondering whether there are unexpected spurs at other frequencies, too, in the whole range from 0...fs/2?

And I'd also test with a few signal frequencies which are not integral fractions of the sampling rate (for some considerations this makes a significant difference - although I guess not in this particular case).

Here is the full spectrum with a 4.5 MHz sine (FFT in dBVrms):


No signal, with V bias:


With Long Mem (signal in time domain is better visible):

[thinkfat]

I could identify the following items:

• crystal oscillator 100.00 MHz
• HA04 27K A8FL: ?
• HImax HX8817ALAG: TCON (Timing Controller Unit)
• CY7C1386D: SRAM
• Altera Cyclone IV: FPGA
• Altera MAX V: CPLD
• 3x IC without imprint

Who knows how these chips work together?

I'd say the "HA04" is a PLL. The passives above the IC are the load caps for the crystal, one resistor across the oscillator inputs, one resistor to limit the current. The passives just below the crystal could be the loop filter.

[gf]

Is this service adjustment done mechanically (potentiometer on the PCB,...) or by a software adjustment with a special proprietary tool?

The adjustment can be easily applied by post-processing the samples in the digital domain, so likely no analog circuitry is involved.

It should be easy for the self-calibration procedure to determine the necessary gain and offset values for aligning the ADCs, so in fact I would be rather surprised if this would require a factory calibration (but who knows )

I take it for granted that you did not forget to run self-calibration, did you?

Here is the full spectrum with a 4.5 MHz sine (FFT in dBVrms):

So you're facing a SFDR of about 34dB, or maybe a little bit more, since the sine wave amplitude was not full-scale yet.
The handbook specifes SFDR >=40dB (but it does not promise significantly more either).

[ Just for comparison the typical SFDR including inverleaving spurs for the HMCAD1511 (which is used in the SDS1000X-E models and also in some other DSOs in this class): 44dBc in dual Ch Mode @500MsPs, 49dBc in single Ch Mode @1000MsPs, and 57dB in quad Ch Mode @250MsPs. ]

[einfachprima]

It should be easy for the self-calibration procedure to determine the necessary gain and offset values for aligning the ADCs, so in fact I would be rather surprised if this would require a factory calibration (but who knows )

I take it for granted that you did not forget to run self-calibration, did you?

I've started the self calibration, but this didn't solve the problem.

[einfachprima]

3x IC without imprint

Those are the memory chips and over the years many CN and CNL models have been upgraded to the CM/CML mem spec with the addition of these chips.
A hunt through the forum should find threads/posts about these upgrades and what Pt# these IC's actually are.

I don't think those are memory chips. Meanwhile I've found two additional chips on the back side of the PCB. I think those are ADCs, 5x dual ADCs, probably AD9288 or similar. I don't know why Siglent has removed the imprint, maybe they are overclocked.

[einfachprima]

Before considering going down this road do the PSU checks on P46......not that it's likely to be the issue but something that should be excluded from investigations.

Today I've checked the voltages of the psu, they are all within the specification.

I think there is nothing more I can do, a factory calibration requires a Fluke generator and a special calibration software.

So I will keep my DSO and use one of the workarounds if needed. Maybe I'll add a new DSO to my wishlist 

Thanks for the discussion and all the hints