Gentlemen, you're right, of course. It may not be strictly related to any real use case. End of discussion?
But I would like to say that the screenshots make me slightly concerned about the instrument's reliability because the voltages are dropping too soon. Perhaps I'm missing something, but with DG811, the process takes an order of magnitude time longer (see the image below). Similar signals, the yellow trace shows the DC waveform which is used to trigger the scope and the other trace is for the same 500 Hz square wave signal. There are almost 11 ms between the first sign of power problem in the left and the last falling edge in the right part of the screen. Both the channels are loaded with 50 Ohm pass-throug terminators. Nevertheless, the yellow line is horizontal, the voltage is not dropping. While on the screenshots above, despite the DC channel is not loaded, the voltage starts gradually decaying in less than 1 ms after the power off event. If enough energy remains inside?
It seems in DG811 the power failure signal is generated well in advance, likely using the information from the primary side of the PS (as it should be done). What if Rigol is more used to design an instrument-grade PSUs in-house (whatever it costs), while it's natural for Siglent to outsource that work to contractors? That also explains why the problem can be seen not with every instrument, as it depends on exact model of the general-purpose PSU, which may vary from batch to batch.
The timing may be directly related to the reliability because the device is controlled by application processor. Typically, a chip like that uses several power voltages and the power on and off sequences are not up to the user. The sequences are stipulated by the chip vendor and must be obeyed. To make it easier to use the chip, the vendor typically provides an auxiliary chip (PMIC) that performs the sequencing automatically. Anyway, for that processor, the sequence takes tens of milliseconds, IIRC.
So on power failure notification, the processor have to gracefully finish with all the business logic and with all the housekeeping tasks like bad block re-allocation, etc., then, optionally, to disable as much peripherals as possible, and finally to instruct the PMIC to start with the power off sequence. That requires reservation of enough energy for PMIC. Otherwise, all the power voltages will be abruptly interrupted, violating the prescribed sequence. The vendor does not qualify the processor for such abnormal cases. Nobody knows what will happen. Perhaps nothing, but it's actually a Russian roulette.