It is explained bit more but unfortunately "scrambled by natural enigma". Our "enigma" is our Finnish language what is said is second difficult after Chinese in world.
In some images there is some english/finglish explanations. But more deep text explanations just with Finnish.
https://siglent.fi/oskilloskooppi-tietoa-sds1004x-e--wfm-speed.html
I am slowly reading through this with help from Google translate. It's very helpful, thank you for writing it!
PS: there is a typo in the second (all yellow) table shown in Figure 1, in the line with t/div= 1ms. Column 6 contains 1G sa/s. It should read 1M sa/s.
Typing mistake corrected, thank you.
Something that would be very useful for me would be a block diagram of the scope. This would help me to construct a good internal model for what it's doing. Just a page or two back you posted a nice block diagram showing the input front end, the DAC for offsets, the ADC feeding the triggering system, but then it gets less precise. Is there a more complete block diagram that shows the acquisition/history/sequence/frame system in some detail?
A few questions regarding the sampling/trigger system: is the ADC always running at 1Gs/sec then decimating afterwards? Is the decimation done before or after the triggering system? When decimating can the scope keep/store more than 8 bits in memory? For example when the scope is acquiring data at 4Msa/a (decimation by factor of 256) in principle one could add the 256 8-bit values to get 16 bit resolution.
There is not this like of functional "block diagram" what also somehow give imagination what user then see when he is using scope.
Also I miss this kind of block diagram not for me but for perhaps for user guidance and counseling.
What I have is just my own made some kind of teaching "flip chart" material in mind what need also explanations by talking when show these images... but they are as they are now. There is some what give rough imagine about sequence, history and so on but they only give very rough basic fuzzy imagine what is going on there.
is the ADC always running at 1Gs/sec then decimating afterwards?
No but yes...
If scope have some special mode it is least possible ADC run some of its lower speed. But example in 1000X-E/U ADC work always full speed what is 1GSa/s in interleaved mode and 500MSa/s in "non interleaved" mode.
There is 1 ADC for 2 channels. When only one is in use ADC run in interleaved mode 1GSa/s, always afaik.
When both channels in use it run "non interleaved" mode and samplerate is 500MSa/s .
(now need remember that if second channel pair ADCserve 2 channels it force also otherchannel pair ADC 500MSa/s.
Note: Also 500MSa/s "non interleaved" mode is interleaved but because this X-E model use it only in 1 or 2 channel mode it can somehow think is is non interleaved. But if look bit more deep it is also interleaved. 1 ADC what is HMCAD1511 have 4x250MSa/s ADC. (example in Rigol 1000Z ADC is shared for all channels and full speed rates are 1Gsa, 500MSa and 250MSa/s. Same "full" samplerates are now also in Siglent X-U)
In Siglent data sheet is one mystery what I hit just short time ago. and I do not know if it is typemistake or what it is. I will later try get more deep info... except if example Performa01 know and see this.
X-U data sheet: Peak detect 2ns.
X-E data sheeet: 4 channels models 2ns, 2 channel models 4ns. Weird. If they are opposite, still weird. Why they are different I do not have idea.
These are two true full speeds in 1000X-E models.
It need note that if example turn one channel in use, time scale for 1ms/div and memory is 14M it use 1GSa/s full speed. If change to 2ms/div it drops to 500MSa/s and in this case ADC still run 1GSa/s so this 500MSa/s is not full speed 500MSa/s but this is decimated 500MSa/s.
As far as I know. Trigger system get always ADC full speed samplerate 1GSa or 500MSa/s. When ever it decimate, it happen after main part of trigger system. If there is decimated samplerate 500MSa/s then every second sample is dropped.
In these 1000 models, in memory is always only 8bit raw ADC data. If with 1GSa/s ADC decimated (and displayed) samplerate is 5MSa/s in mean that it take 1 sample and drop away 199 samples. It do not look what is "best" sample or what is average in this 200 samples group. Stored byte is just this byte what is every 200th byte in order in queue. This in normal mode.
In Peak detect mode it look what is highest in decimation "group" (example in this 200 sample group) and take this one to acq. memory (and loose it time position in original ADC data.).
SDS2000XPlus is different. It can produce more than 8bit in high resolution mode and of course it then consume also more memory.
So in short.
ADC work always full speed what depends how many channels in use.
Trigger engine listen this non decimated ADC stream.
If need decimate, it happen after then before acquisition memory what have always 8bit level information.
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