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Sniffing the Rigol's internal I2C bus

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cybernet:

--- Quote from: alank2 on December 10, 2013, 11:27:08 pm ---Dave's teardown talks about a Lattice Mach IO PLD - any idea what would be the likely way the Blackfin would communicate with this?

--- End quote ---

via SPORT

alank2:

--- Quote from: cybernet on December 10, 2013, 11:59:05 pm ---via SPORT

--- End quote ---

I've decoded the LDR streams and then loaded them into IDA.  I can see about a dozen subs that contain SPORT registers, but no SPORT0_RX or SPORT1_RX...

cybernet:
study the bfin manual with regards to DMA ;)

cosmos:

--- Quote from: alank2 on December 10, 2013, 11:27:08 pm ---Dave's teardown talks about a Lattice Mach IO PLD - any idea what would be the likely way the Blackfin would communicate with this?

--- End quote ---

Maybe I am blind but I don't see any candidates for a Lattice PLD (except maybe the small clock generation device next to the ADC and sample FPGA).
When in the teardown was this? and was he talking about the DS2k?

cybernet:

--- Quote from: cosmos on December 11, 2013, 01:05:45 am ---
--- Quote from: alank2 on December 10, 2013, 11:27:08 pm ---Dave's teardown talks about a Lattice Mach IO PLD - any idea what would be the likely way the Blackfin would communicate with this?

--- End quote ---

Maybe I am blind but I don't see any candidates for a Lattice PLD (except maybe the small clock generation device next to the ADC and sample FPGA).
When in the teardown was this? and was he talking about the DS2k?

--- End quote ---

keyboard/leds on the frontpanel

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