Products > Test Equipment
Sniffing the Rigol's internal I2C bus
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Carrington:

--- Quote from: JLM on December 23, 2013, 01:32:59 pm ---After upgrade, my options list shows both "200 MHz bandwidth" and "300 mhz bandwidth".  Is that normal?  Can I and should I delete the 200, and if so, how?

--- End quote ---
In my case the same, I do not know if this can be a problem.
alank2:

--- Quote from: JLM on December 23, 2013, 01:32:59 pm ---After upgrade, my options list shows both "200 MHz bandwidth" and "300 mhz bandwidth".  Is that normal?  Can I and should I delete the 200, and if so, how?

--- End quote ---

Did you use DSGH ?  That should have 300/can/trig/decod/56m
alank2:
One of the memory registers does confirm 32M of SDRAM for program memory (0x00000000 - 0x01ffffff).

The blackfin also has 4 async memory areas mapped at: 0x20000000-0x200fffff, 0x20100000-0x201fffff, 0x20200000-0x202fffff, 0x20300000-0x203fffff.  I can see some memory pointers pointing to 0x201exxxx, 0x2020xxxx, 0x2024xxxx.

Each of these is only a 1M range.  How are these async memory areas normally used?  When more than 1M is available it is banked somehow?  I don't see any banking capability in the blackfin for this unless I am missing something.

Could the aquire memory (ddr2) also be accessed via this async memory?
Carrington:

--- Quote from: apelly on December 23, 2013, 07:53:08 am ---These will have to do for now... The 'scpoe's still open, so can take more, but even a linux buff like me needed to look up a quick way to resize pics.
Just let me know what you want to see.

--- End quote ---
Thank you so much, the parts in which I am interested are these:

https://www.eevblog.com/forum/testgear/rigol-ds2000-hardware-version-2-0/msg270218/#msg270218
https://www.eevblog.com/forum/testgear/rigol-ds2000-hardware-version-2-0/msg272842/#msg272842

Cheers.
m-joy:


Did you use DSGH ?  That should have 300/can/trig/decod/56m
[/quote]

I thought DSHH should be used...?
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