Products > Test Equipment
Sniffing the Rigol's internal I2C bus
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cybernet:
currently on another track that will hopefully make stuff easier in the future - esp no need for JTAG anymore ;-)


--- Code: ---bfin> bdinfo
U-Boot      = U-Boot 2013.10 (Dec 30 2013 - 18:01:24)
CPU         = bf526-0.0
Board       = bf526-ezbrd
VCO         =    400 MHz
CCLK        =    400 MHz
SCLK        =    100 MHz
boot_params = 0x00000000
memstart    = 0x00000000
memsize     = 0x02000000
flashstart  = 0x20000000
flashsize   = 0x01000000
flashoffset = 0x00000000
ethaddr     = 02:80:ad:20:31:e8
ip_addr     = 192.168.0.15
baudrate    = 57600 bps
bfin> flinfo

Bank # 1: CFI conformant flash (16 x 16)  Size: 16 MB in 71 Sectors
  AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x227E2101
  Advanced Sector Protection (PPB) enabled
  Erase timeout: 4096 ms, write timeout: 1 ms
  Buffer write timeout: 3 ms, buffer size: 64 bytes

  Sector Start Addresses:
  20000000   RO   20020000   RO   20040000   RO   20060000   RO   20080000   RO
  200A0000   RO   200C0000        200E0000        20100000        20120000     
  20140000        20160000        20180000        201A0000        201C0000     
  201E0000        20200000        20220000        20240000        20260000     
  20280000        202A0000        202C0000        202E0000        20300000     
  20320000        20340000        20360000        20380000        203A0000     
  203C0000        203E0000   RO   20400000   RO   20420000   RO   20440000   RO
  20460000   RO   20480000   RO   204A0000        204C0000        204E0000     
  20500000        20520000        20540000        20560000        20580000     
  205A0000        205C0000        205E0000        20600000        20620000     
  20640000        20660000        20680000        206A0000        206C0000     
  206E0000        20700000        20720000        20740000        20760000     
  20780000        207A0000        207C0000        207E0000        20800000     
  20820000   RO   20840000   RO   20860000   RO   20880000   RO   208A0000   RO
  208C0000   RO
bfin> reginfo

System Configuration registers

PLL Registers
PLL_DIV:   0x0004   PLL_CTL:      0x2000
PLL_STAT:  0x00a2   PLL_LOCKCNT:  0xffff
VR_CTL:    0x70f0

EBIU AMC Registers
EBIU_AMGCTL:   0x00f9
EBIU_AMBCTL0:  0xbbc3bbc3   EBIU_AMBCTL1:  0xb6ab77c3

EBIU SDC Registers
EBIU_SDRRC:   0x0fff   EBIU_SDBCTL:  0x0013
EBIU_SDSTAT:  0x0000   EBIU_SDGCTL:  0x8011998d


--- End code ---
marmad:
Just to keep owners that aren't reading the DS2000 review thread informed:

More bugs keep getting discovered when running the 300MHz option on HW v.1 DS2000 models (I just posted another here).

Whether those bugs exist for HW v.2 or A-model owners, I couldn't say - but considering that we've found a few of them - and that on HW v.1 models the BW only seems to increase by ~60MHz (to somewhere between ~280 - 300MHz), you might want to consider if the advantages outweigh the disadvantages before installing the option (on HW v.1)
m-joy:

--- Quote from: marmad on December 30, 2013, 07:29:12 pm ---Just to keep owners that aren't reading the DS2000 review thread informed:

More bugs keep getting discovered when running the 300MHz option on HW v.1 DS2000 models (I just posted another here).

Whether those bugs exist for HW v.2 or A-model owners, I couldn't say - but considering that we've found a few of them - and that on HW v.1 models the BW only seems to increase by ~60MHz (to somewhere between ~280 - 300MHz), you might want to consider if the advantages outweigh the disadvantages before installing the option (on HW v.1

--- End quote ---

But 200MHz works fine?
marmad:

--- Quote from: m-joy on December 30, 2013, 07:42:11 pm ---But 200MHz works fine?

--- End quote ---

Sure - every version of the DS2000 hardware has been designed to work to 200MHz-2ns/div.
Git:

--- Quote from: Carrington on December 28, 2013, 03:01:49 pm ---
--- Quote from: tirulerbach on December 28, 2013, 02:36:41 pm ---Hello,
Just to make sure: Is the JTAG-port on DS2202A at 3.3 Volt?

--- End quote ---
Yes, I think.

--- End quote ---

It shouldn't matter anyway,  your JTAG box should power its output stage from the target machines supply. Some, if not most, are happy from 1.8V to 5V.

Git
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