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SynthUSBII USB RF Signal Generator & CPDETLS-4000 RF Power Detector

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TomC:
This post describes the first of a series of experiments where I try to explore the effect of harmonics on the behavior of LBSD detectors such as the one used in the CPDETLS-4000. On this first experiment I'd like to look at harmonics that vary in phase in respect to the fundamental, for example, as the harmonics associated with AM modulation could be expected to behave.

The experiment I have in mind came to me after reading "Characteristics and Applications of Diode Detectors" by Ron Pratt:

www.hparchive.com/seminar_notes/Pratt_Diode_detectors.pdf

On page 26 of this document there is a graph titled "Error Produced by 2nd Harmonic Predicted by Simple Model", see attachment #1. The experimental test described below is meant to help visualize with actual waveforms and absolute values the analysis described on this page.

The steps below describe how I simulated a time domain signal with the characteristics of the frequency domain graph illustrated on the left hand side of #1. This is then used to help predict the behavior of a perfect LBSD detector operating in the linear region (No junction voltage drop and an output voltage that corresponds perfectly to the peak voltage of the input signal) when this signal is applied to its input:

   1. I used my dual channel AWG to generate two signals, a 10MHz 2Vpp (10dBm) sine wave used to represent the fundamental and a 20MHz 200mVpp (-10dBm) sine wave used to represent a 2nd harmonic. The -20dBc ratio was chosen so it would coincide with the model depicted by attachment #1.

   2. I fed the AWG's output signals to CH1 & CH2 of my DSO and used the DSO's math function to add the fundamental and the second harmonic. The resulting trace (green trace on my DSO) represents the way that the combined signals would appear at the detector's input.

   3. While observing the DSO's green trace, I slowly changed the phase of the harmonic in respect to the fundamental with the AWG's phase control. The high and low extremes that corresponds to the graph on the right hand side of #1 occur when the positive peaks are in phase, and when the negative peaks are in phase, see attachment #2.

Assuming that the power detector is operating in the linear region, uses a single diode arrangement, and the input signal is connected directly to the diode, then the detector's output should be very close to the peak voltage of the green trace. The peak voltage of a signal can be used to accurately derive its power level if the signal is a clean sine wave, for example, if the harmonic wasn't present the peak voltage in this case would be around 1V and the dBm level could be calculated with the formula:

   dBm = 10log_10[(Vpp)^2 / (0.008R)] = 10log_10[(2^2 / 0.4)] = 10dBm.

However, with the harmonic present the extremes produce 1.10V and 0.9V respectively (see #2). So the reported dBm levels are:

   dBm = 10log_10[(2.2^2 / 0.4) = 10.83dBm
   dBm = 10log_10[(1.8^2 / 0.4) = 9.085dBm

Since the expected power level is 10dBm (10mW), but we could end up with as much as 10.83dBm (12.1mW), or as little as 9.085dBm (8.1mW), the power percentage error can be determined as follows:

   (12.1 - 10) / 10 x 100 = 21%
   ( 8.1 - 10) / 10 x 100 = -19%

And the voltage percentage error can be determined as follows:

   (1.1 - 1) / 1 x 100 = 10%
   (0.9 - 1) / 1 x 100 = -10%

The above values represent the worst case error caused by the presence of the harmonic. The uncertainty range in dB can be determined by subtracting the expected value from each extreme:

   10.83dBm - 10dBm = 0.83dB
   9.085dBm - 10dBm = -0.92dB

Alternatively, it could be determined by converting the ratio of the power levels to dB:

   dB = 10log_10(P_1 / P_2)
   dB = 10log_10(12.1 / 10) = 0.83dB
   dB = 10log_10( 8.1 / 10) = -0.92dB

These simulation results perfectly coincide with the values given in #1.


Attachment #1 - Graph of the error produced by a 2nd harmonic depending on the region of operation of the diode detector. This came from an HP document written by Ron Pratt. I've seen almost identical graphs on other documents but I couldn't verify the cited values with the given formulas. However, the formulas given in this version worked out just fine for me.


Attachment #2 - Simulation of the effect of a 2nd harmonic on the fundamental starting when the positive peaks are in phase and ending when the negative peaks are in phase. Channel 1 of the AWG is set to 10MHz 2Vpp, Channel 2 is set to 20MHz 200mVpp. Each AWG channel is connected to the corresponding DSO channel via a feed-through 50 ohm terminator. The green trace was produced by adding the fundamental (red trace) to the harmonic (yellow trace) using the DSO's math function. The AWG's phase control allows the user to adjust the phase from 0 to 360 degrees.

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Next I'll try to combine these signals using a BNC T and connect them to the CPDETLS-4000.


Edit: I wasn't happy with the way Attachment #2 looked when displayed on my PC monitor. The resolution wasn't the same as when I tried it off-line, so I added single image attachments #2a & #2b for anyone having difficulty viewing the details on attachment #2.

TomC:
This post is the sequel to post #20. Its the second of a series of experiments where I try to explore the effect of harmonics on the behavior of LBSD detectors such as the one used in the CPDETLS-4000. On this experiment I use a standard BNC T to combine the signals from the two AWG channels. See post #20 for details of how the AWG was setup.


Attachments #1 & #2 - Here the BNC T is directly connected to the DSO's CH1. The AWG is setup the same as it was for post #20. Since the AWG channels terminate each other via the BNC T, there is no need for the 50 ohm feed-through terminators used on post #20. The CH1 display is nearly identical to the green trace produced by the DSO's math function on post #20. For calculations I'm using the values from the measurements at the bottom left of the screen instead of the cursors used on post #20. On this DSO Vp = Vpp, Vt = Vtop, and Vk = Vrms.

As in the previous post, if the harmonic wasn't present the peak voltage in this case would be around 1V and the dBm level could be calculated with the formula:

   dBm = 10log_10[(Vpp)^2 / (0.008R)] = 10log_10[(2^2 / 0.4)] = 10dBm.

However, with the harmonic present the extremes produce 1.10V and 0.9V respectively as indicated by Vt. So the reported dBm levels are:

   #1. dBm = 10log_10[(2.2^2 / 0.4) = 10.83dBm
   #2. dBm = 10log_10[(1.8^2 / 0.4) = 9.085dBm

Since the expected power level is 10dBm (10mW), but we could end up with as much as 10.83dBm (12.1mW), or as little as 9.085dBm (8.1mW), the power percentage error can be determined as follows:

   #1. (12.1 - 10) / 10 x 100 = 21%
   #2. ( 8.1 - 10) / 10 x 100 = -19%

And the voltage percentage error can be determined as follows:

   #1. (1.1 - 1) / 1 x 100 = 10%
   #2. (0.9 - 1) / 1 x 100 = -10%

The above values represent the worst case error caused by the presence of the harmonic. The uncertainty range in dB can be determined by subtracting the expected value from each extreme:

   #1. 10.83dBm - 10dBm = 0.83dB
   #2. 9.085dBm - 10dBm = -0.92dB

Since the DSO provides a Vrms value for CH1 we can also calculate the "actual" dBm value of the combined signal:

   dBm = 10log_10[(Vrms)^2 / (0.001R)]
   #1. dBm = 10log_10[0.7178^2 / 0.05] = 10.13dBm
   #2. dBm = 10log_10[0.7165^2 / 0.05] = 10.11dBm

Note: In theory the Vrms value should be the same regardless of the phase but since the DSO reports slight differences I used the exact reported values for the calculations.


Attachments #3 & #4 - Here the BNC T is connected to the DSO's CH1 via a 50 ohm feed-through terminator. The AWG is setup the same as for attachments #1 & #2 except that the "load" setting is set to 25 ohms instead of 50 ohms. This is necessary because each channel was already seeing a 50 ohm load via the BNC T, the 50 ohm feed-through is in parallel so the load seen by each channel is now 25 ohms. Note that the DSO's display is nearly identical to what we got for #1 and #2 except for a slight difference in the Vrms values, again, in theory, these should all be the same. However, for completeness sake, here are the calculations:

   #3. dBm = 10log_10[0.7197^2 / 0.05] = 10.15dBm
   #4. dBm = 10log_10[0.7188^2 / 0.05] = 10.14dBm

With this step of the experiment the only thing we achieved is to verify that the AWG setup behaves as expected in a 50 ohm system. On the next step we'll remove the 50 ohm feed-through terminator and connect the CPDETLS-4000 in its place. If the DSO reports any level changes we'll know that is not the AWG settings and that the reason is that the CPDETLS-4000's impedance is not quite 50 ohms.


Attachments #5 & #6 - Here the BNC T is connected to both CH1 of the DSO and to the CPDETLS-4000 via an SMA T. The CPDETLS-4000 DC output is connected to the DMM via a short RG316 cable. For this step of the experiment the DSO connection is not essential, we are mostly interested on the CPDETLS-4000's DC output. However, its interesting to see if the DSO reports different signal levels with this connection just to assess how well the detector's input matches the system's impedance. In addition, it helps verify that the AWG phase setting is correct for the readings at the two extremes.

   #5. CPDETLS-4000's DC output = 787.8mV reported by the DMM.
       This translates to 2150.5mVpp or 10.63dBm as per the datasheet's calibration points.

       Since the DSO reports signal levels > #3, this means that the CPDETLS-4000's impedance is > 50 ohm.
       These signals are not used for any other calculations
 
   #6. CPDETLS-4000's DC output = 614.1mV reported by the DMM.
       This translates to 1764.1mVpp or 8.91dBm as per the datasheet's calibration points.

       Since the DSO reports signal levels > #4, this means that the CPDETLS-4000's impedance is > 50 ohm.
       These signals are not used for any other calculations
 
Now let's go through the calculations we did for #1 & #2 again so that we can compare the behavior of the CPDETLS-4000 to the perfect detector previously envisioned.

Again, if the harmonic wasn't present the expected peak voltage would be around 1V and the expected dBm level is calculated with the formula:

   dBm = 10log_10[(Vpp)^2 / (0.008R)] = 10log_10[(2^2 / 0.4)] = 10dBm.

Note that 10dBm is the level that we expect from the perfect detector. This is probably different from what you would get with the CPDETLS-4000. From previous experiments we know that it under reports at this power level, so it would probably report around 9.9dBm. However, for the comparison calculations below we want to use the same level used for the perfect detector.

With the harmonic present the extremes produce 2.1505Vpp and 1.7641Vpp respectively as indicated by the datasheet's calibration points. So the reported dBm levels are:

   #5. dBm = 10log_10[(2.1505^2 / 0.4) = 10.63dBm (compared to: 10.83dBm)
   #6. dBm = 10log_10[(1.7641^2 / 0.4) =  8.91dBm (compared to:  9.085dBm)

Since the expected power level is 10dBm (10mW), but we could end up with as much as 10.63dBm (11.6mW), or as little as 8.91dBm (7.8mW), the power percentage error can be determined as follows:

   #5. (11.6 - 10) / 10 x 100 =  16% (compared to:  21%)
   #6. ( 7.8 - 10) / 10 x 100 = -22% (compared to: -19%)

And the voltage percentage error can be determined as follows:

   #5. (1.075 - 1) / 1 x 100 =   7.5% (compared to:  10%)
   #6. (0.882 - 1) / 1 x 100 = -11.8% (compared to: -10%)

The above values represent the worst case error caused by the presence of the harmonic. The uncertainty range in dB can be determined by subtracting the expected value from each extreme:

   #5. 10.63dBm - 10dBm = 0.63dB (compared to:  0.83dB)
   #6. 8.91dBm - 10dBm = -1.09dB (compared to: -0.92dB)

Since the DSO provides a Vrms value for CH1 we can also calculate the "actual" dBm value of the combined signal:

   #3. dBm = 10log_10[0.7197^2 / 0.05] = 10.15dBm
   #4. dBm = 10log_10[0.7188^2 / 0.05] = 10.14dBm

As indicated, these "actual" dBm values came from the DSO readings obtained on #3 & #4. As previously stated, We can't use the DSO readings from #5 & #6 for any of these calculations, they are inaccurate due to the CPDETLS-4000's impedance.


Some things about the CPDETLS-4000 that I learned or verified with this experiment:


   1. It uses a single diode arrangement. This is evident because there is a large difference in reported values between the extreme where the positive peaks are in phase and the extreme where the negative peaks are in phase.

Some power detectors use two diodes in a push-pull arrangement. In this case the reported value is the average of the positive and negative peaks, so there wouldn't be a significant difference between the extremes. One advantage of this dual diode arrangement is that even in the linear region, when even harmonics are present the reported dBm value is much closer to the "actual" value. For example, in the case of #3 & #4 the reported value would have been about 1/2 the Vpp or around 1.01V. So the dBm value would be:

   dBm = 10log_10[(Vpp)^2 / (0.008R)] = 10log_10[(2.02^2 / 0.4)] = 10.09dBm

Much closer to the "actual" dBm value which my DSO reports as somewhere between 10.11dBm and 10.15dBm.


   2. The diode is wired so that it detects the positive peaks. This is evident because the output DC level is always positive. In addition, this level is higher for the extreme where the positive peaks are in phase.

Some power detectors are wired so that they detect the negative peaks, in some cases this a feature that can be specified when the device is ordered.


   3. The input signal is not directly connected to the diode. This is evident because there is a large difference between the output DC level and peak voltage of the input signal. To me this indicates that there is significant attenuation before the signal is applied to the diode, possibly caused by the components of an impedance matching network.


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Next I plan to do some experiments involving square waves.

TomC:
When I started this topic one of the main objectives was to measure and report the output levels of the SynthUSBII at different frequencies. At the time I didn't have appropriate equipment to get accurate results. Now that I have a Spectrum Analyzer, I decided to add that last bit of information to this topic. The SynthUSBII was directly connected to the SA's input (no cables) when the readings in the attached photos were obtained. The four traces represent the 4 output levels available on the SynthUSBII.

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