Products > Test Equipment
Tektronix 2465 MAME emulation
siggi:
--- Quote from: MarkL on March 03, 2023, 11:39:46 pm ---I did some experimenting with creating a number of sweeps between TSO polls, and it appears the count is returned in the high order byte of TSO (TSO16..TSO9). The count maxes out at 0x99 after decimal 99 sweeps.
--- End quote ---
That's awesome - also how strange to do this in BCD-ish. I guess someone decided that'd be preferable to writing binary to decimal conversion, though I'm not aware of any place this sweep count is ever displayed.
--- Quote from: MarkL on March 03, 2023, 11:39:46 pm ---What's very strange is the binary sequence used to represent the decimal value in each of the nibbles. The decimal representation for both nibbles goes like this:
Nibble Nibble
Value (hex) (binary)
----- ------ --------
0 0 0000
1 1 0001
2 2 0010
3 3 0011
4 6 0110
5 7 0111
6 C 1100
7 D 1101
8 8 1000
9 9 1001
I've shown the binary in the hopes that maybe someone else can spot an encoding scheme, a pattern, or relate this sequence back to a design decision in the chip. The only pattern I see is the 3 high order bits are in groups of 4 vertical 1's, offset by two steps to the other two groups. And the low order bit is just alternating.
--- End quote ---
How bizarre! Apparently there are a multitude of BCD encodings, but I couldn't find a match with any of the encodings on Wikipedia.
--- Quote from: MarkL on March 03, 2023, 11:39:46 pm ---What does the firmware do with the sweep count?
--- End quote ---
I haven't taken a look, though in emulation it's easy enough to set a read watchpoint on a memory location.
siggi:
--- Quote from: siggi on March 04, 2023, 04:43:27 pm ---
--- Quote from: MarkL on March 03, 2023, 11:39:46 pm ---What does the firmware do with the sweep count?
--- End quote ---
I haven't taken a look, though in emulation it's easy enough to set a read watchpoint on a memory location.
--- End quote ---
I set a watchpoint on $73 read, then fiddled a bit. Aside from the memory check on startup, I didn't get a single hit on read. I even stepped through CAL 01/02/03/04, where the vertical calibration hit LIMITs and I now have an uncalibrated scope, guesss I need to throw away the EAROM settings :).
It's still possible that the value is used in particular modes, or perhaps from options. I didn't play with the B sweep as a case in point.
On the 2467/2465[AB], the trace and readout intensity is under software control. On those I could see the firmware modulating the A/B-sweep brightness as a function of how often it's sweeping?
siggi:
--- Quote from: MarkL on March 02, 2023, 09:15:01 pm ---Here are the frames during TEST 05.
...
I don't know how helpful this will be by itself. If you need the TSO values in the context of other pins, or other signals somewhere, please let me know.
--- End quote ---
So I pulled the dump, deciphered the sweep counts given the information you ferreted out, and the results seem impossible. More below.
One thing I see is that TSO6 (0x20) is set whenever the sweep count is non-zero in your dump. I think, however, that this bit logically has to mean either triggered or "at least one sweep started". Consider the case where the sweep is super slow, like 500ms/DIV, in which case the sweep count will increment ever 5s. However, the TRIG'D light lights up at the start, and stays lit until the sweep is done.
So, I think the TSO register has to have some kind of latching "triggered" or "sweep started" bit, which is almost certainly TSO6 for the A sweep. There almost certainly has to be a "sweep in progress" flag as well. Likely these flags exist for both A and B sweeps? If so, that'd account for 4 out of 8 bits, with the 5th bit being "!single sequence in progress".
Now, looking at the sweep counts and trigger flags, there are several cases where the counts are "impossibly" high:
--- Code: ---dt=3.40ms, v=0010110001110011, ct=26 *T*
dt=2.50ms, v=0010001001111111, ct=22 *T*
dt=11.30ms, v=1111111111111111, ct=NANA *T*
dt=2.10ms, v=0001110001110011, ct=16 *T*
dt=2.30ms, v=0001100001110011, ct=18 *T*
dt=2.50ms, v=0010000101110011, ct=21 *T*
dt=1.60ms, v=0001011001110011, ct=14 *T*
dt=2.50ms, v=0010000101110011, ct=21 *T*
dt=2.30ms, v=0001100001110111, ct=18 *T*
dt=2.50ms, v=0010000101110101, ct=21 *T*
dt=1.60ms, v=0001011001110101, ct=14 *T*
dt=3.90ms, v=0011001001110111, ct=32 *T*
dt=2.50ms, v=0010000101110011, ct=21 *T*
dt=1.70ms, v=0001011001110011, ct=14 *T*
dt=2.50ms, v=0010000101110111, ct=21 *T*
--- End code ---
This lists the delta time between TSO value reads, and as you see there are as many as 32 sweep counts in a 3.9ms interval, which corresponds to an 8.2kHz sweep frequency, AND the triggered flag is set. The problem is that I can't think of any way for the hardware to route or generate an 8kHz signal to the triggers.
So, what's up with that?
MarkL:
--- Quote from: siggi on March 04, 2023, 05:16:13 pm ---...
On the 2467/2465[AB], the trace and readout intensity is under software control. On those I could see the firmware modulating the A/B-sweep brightness as a function of how often it's sweeping?
--- End quote ---
It could be the sweep count capability was "for future use" and never used in the 2465. I have a 2445A which also has the digital intensity control, so I could look there to see what it's doing.
--- Quote ---...
This lists the delta time between TSO value reads, and as you see there are as many as 32 sweep counts in a 3.9ms interval, which corresponds to an 8.2kHz sweep frequency, AND the triggered flag is set. The problem is that I can't think of any way for the hardware to route or generate an 8kHz signal to the triggers.
So, what's up with that?
--- End quote ---
Hmmm. I will set up an SPI trigger to look for high sweep count values to see if I can catch any pins that might be supplying something n the 8kHz range. The chip does have a 5MHz clock input, so it could be generating something internally, possibly initiated by a command that puts it in a test mode.
MarkL:
--- Quote from: MarkL on March 04, 2023, 10:50:53 pm ---...
Hmmm. I will set up an SPI trigger to look for high sweep count values to see if I can catch any pins that might be supplying something n the 8kHz range. The chip does have a 5MHz clock input, so it could be generating something internally, possibly initiated by a command that puts it in a test mode.
--- End quote ---
Ok, there is truly 33 or 34 sweeps occurring between many of the TSO polling intervals by looking at the A gate output on the back (I've been calling it the A sweep output). It's hard to say if something is sending those sweeps to the chip or if it's generating them itself for testing. The 8.5kHz signal is present on a number of pins: 1, 6, 10, 13, 15, and 37, and is sometimes mixed in with other pulses and clocking.
I think the chip is generating it itself. It has the 5MHz clock input, so it has a source. It's also responsible for the CAL output, so arbitrary clock generation in this chip already exists in at least one place.
Is this important? I can capture all the pins above at once with the scope or the Saleae if you need to know what threy're doing, but maybe I should focus on the other bits in TSO?
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