Products > Test Equipment
Tektronix 2465 MAME emulation
siggi:
--- Quote from: MarkL on March 05, 2023, 12:57:19 am ---I think the chip is generating it itself. It has the 5MHz clock input, so it has a source. It's also responsible for the CAL output, so arbitrary clock generation in this chip already exists in at least one place.
--- End quote ---
Yeah, the holdoff function is also highly programmable. The input register has five bits for trigger holdoff, plus it's adjustable with the DAC. Maybe this is just a really fast autosweep - though I'm surprised to see what I've termed A-triggered bit set for those sweeps. There is a "FREE RUN" bit in the trigger dies, so maybe that's used here - I'll play with the emulator a bit, see if I can figure out what the various modes are.
--- Quote from: MarkL on March 05, 2023, 12:57:19 am ---Is this important? I can capture all the pins above at once with the scope or the Saleae if you need to know what threy're doing, but maybe I should focus on the other bits in TSO?
--- End quote ---
I'm not sure that this is important, though I suspect it might be necessary to understand this in due course for the emulator to pass the 05 tests. I'm more interested to know about the bits in the TSO, particularly if there are e.g. "[AB] sweep in progress" and "[AB] triggered" bits.
siggi:
--- Quote from: siggi on March 05, 2023, 03:45:24 pm ---
--- Quote from: MarkL on March 05, 2023, 12:57:19 am ---Is this important? I can capture all the pins above at once with the scope or the Saleae if you need to know what threy're doing, but maybe I should focus on the other bits in TSO?
--- End quote ---
--- End quote ---
So the "Theory of Operation" section of the service manual has this to say:
Trigger and Sweep Activity (Status)
The activity of the Trigger and Sweep circuits, as indicated by the /SGA, /SGB, /TSA, and /TSB lines, is reported to the Microprocessor via the TSO (trigger status output) line when clocked by the TSS (trigger status strobe) signal.
So /TSA and /TSB are inputs to the Display Sequencer, and not outputs from it, as I had surmised. Presumably these four account for 4 bits of the TSS, with the a fifth bit being the "not single sequence underways".
--- Quote from: siggi on March 05, 2023, 03:45:24 pm ---I'm not sure that this is important, though I suspect it might be necessary to understand this in due course for the emulator to pass the 05 tests.
--- End quote ---
Mkay, I think this is simply a really fast auto sweep. I'm still trying to figure out how auto sweep works, though by diffing the register settings for the same sweep in AUTO vs NORM I see this:
--- Code: --- diff AUTO.txt NORM.txt
35,37c35,37
< :trig_a: 0xFA
< -TM0-1, Not Trigger Mode: 1(FAST_COMPARE)
< -FR, Not Free Run, Continuous Trigger Gate: 0
---
> :trig_a: 0xFF
> -TM0-1, Not Trigger Mode: 3(SWEEP)
> -FR, Not Free Run, Continuous Trigger Gate: 1
44,45d43
--- End code ---
So in other words, AUTO is FAST_COMPARE mode with the continuous trigger gate, whereas NORM is SWEEP mode with no continuous trigger gate.
I guess in FAST_COMPARE, the sweep triggers on the first of /TGA|/TRIG or THO - or maybe the sweep triggers on the falling edge of THO on auto sweep?
MarkL:
Ok, this took a bit (pun intended?) of playing to come up with a model of what's happening in TSO. At the moment it fits my current set of observations, but you'll probably find something that's inconsistent.
Sorry I'm not including data dumps and screen shots; there were just too many combinations to document it all. If there's a particular operating condition(s) you'd like to see, please let me know and I will grab a screen and data capture.
Current guess at lower TSO bits 3/9/2023
----------------------------------------
"now" refers to the interval when TSO is being read out (polled).
TSO8..TSO1
----------
0xxx xxxx /SGB remained high since last poll
1xxx xxxx /SGB transitioned low after last poll, or is low now
x01x xxxx /SGA pin is low now
x11x xxxx /SGA pin toggled since last poll
x10x xxxx /SGA pin is high now
xxx0 1xxx /TSB pin is low now
xxx1 1xxx /TSB pin toggled since last poll
xxx1 0xxx /TSB pin is high now
xxxx x01x /TSA pin is low now
xxxx x11x /TSA pin toggled since last poll
xxxx x10x /TSA pin is high now
xxxx xxx0 SNGL mode not READY (sweep done)
xxxx xxx1 All other trigger modes
Other notes:
- /TSB continues to indicate B trigger status, whether B trigger is in
use or not.
- /TSA is continuously high or low when free-running in AUTO mode
(*not* AUTO LVL mode), depending on if A trigger voltage level is
completely above or below the input signal.
siggi:
--- Quote from: MarkL on March 09, 2023, 06:33:20 pm ---
Current guess at lower TSO bits 3/9/2023
----------------------------------------
"now" refers to the interval when TSO is being read out (polled).
TSO8..TSO1
----------
0xxx xxxx /SGB remained high since last poll
1xxx xxxx /SGB transitioned low after last poll, or is low now
x01x xxxx /SGA pin is low now
x11x xxxx /SGA pin toggled since last poll
x10x xxxx /SGA pin is high now
xxx0 1xxx /TSB pin is low now
xxx1 1xxx /TSB pin toggled since last poll
xxx1 0xxx /TSB pin is high now
xxxx x01x /TSA pin is low now
xxxx x11x /TSA pin toggled since last poll
xxxx x10x /TSA pin is high now
xxxx xxx0 SNGL mode not READY (sweep done)
xxxx xxx1 All other trigger modes
--- End quote ---
Wow, this is awesome. Just to make sure I understand correctly: the x11x (toggled) state is latching - e.g. if the pin in question has toggled, it's going to stay in the x11x state?
MarkL:
--- Quote from: siggi on March 09, 2023, 09:34:03 pm ---...
Wow, this is awesome. Just to make sure I understand correctly: the x11x (toggled) state is latching - e.g. if the pin in question has toggled, it's going to stay in the x11x state?
--- End quote ---
Cool - glad it's useful!
The x11x pattern is latched for one poll cycle, then on the next poll it shows the "now" pin state again. The x11x state I think is to let the processor know a transition happened between polls on /SGA. /TSA, or /TSB.
If not clear I can set up an example and post the capture.
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