Products > Test Equipment
Tektronix TDS744 CRT to LCD color converter FPGA module DIY
ltarjanyi75:
Hi Vincent!
Do you have any progress of your LCD conversion? How the new schematic/PCB does work, if you built it? Could you manage the power supply from J5 connector of the scope board?
In your first schematic you planned to use some signal level shifter, which you changed to serial resistors as I can see. Does this work safely with the FPGA? How did you calculated the necessary resistor value?
Do you power the FPGA in your setup from the RAMDAC? On the schematic I can see that +5V is connected to J6 and also to J8 (which goes to FPGA), so I assume you power the FPGA from RAMDAC pins. Am I right.
What about the 3.3V, do you use external power supply for this?
Thanks,
Laszlo
TerrySt:
Laszlo,
I am also looking into using the excellent vhdl code from Vincent. I have a TDS 524A that I want to convert to LCD, so I have been looking into some of those same questions.
For the level shifter, I think it depends on the FPGA you intend to use. The older versions apparently have clamping diodes on the inputs to prevent the input level from rising more then one diode drop above the VCC for the IO bank of the FPGA. So the resistor just limits the input current to the pin . (5V - 3.3V - 0.6V )/ 330 Ohms = 3 mA into the pin, which is a safe current. But I think the newer FPGAs do not have the clamping diodes. I can't find any proof of that in the data sheets, but I found a discussion that said they dropped the clamp diodes in favor of having hot swap capability on the inputs. The resistor value is a compromise between being high enough to limit the input current but not so high that the slew rate of the signal is slowed too much.
I am using a newer FPGA (Spartan 7) so I chose to use a level shifter IC. Also, I didn't like the idea of loading the o'scope logic signals so heavily on the high levels, nor the slowing of the signals that the resistor would cause. It probably works fine on an older Spartan, but I prefer a more conservative approach using level shifters (74LCX541D).
I looked at other approaches. A resistor divider would work (but also loads and slows the signals). Or the approach used by https://bastelblog.runlevel3.de/en/restore/ds1250-fram-replacement/ uses a red led and a schottky diode on each signal line. It works well (I built the FRAM board for my scope) and is pretty small and easy to include in the design.
But in the end, I think I will just use the level shifter IC.
For the power supplies, you can probably get away with using the 5V supply from the scope at the RAMDAC chip to power the FPGA board.
But again, I decided to be conservative. I am planning on using the G065VN01 V2 LCD panel. It requires 3.3V for the logic at 300mA max (I measured 220mA on mine) and 12V for the LCD backlight at 250mA. Then you need whatever current the FPGA board you are using will draw. Mine needs 5V. The current is probably 200 to 300mA or so, but I haven't checked it while running the full vhdl code yet.
Since I needed 12V for the lcd panel anyway, I decided to use a small smps powered from the 25V at the connector on the oscope that was used to drive the CRT power supply. That gives me 12V in a small package (OKI-78SR-12/1.0-W36H-C, DigiKey 811-3294-ND). Then I used the 5V version (OKI-78SR-5/1.5-W36H-C, DigiKey 811-2692-ND) also powered from the 25V o'scope supply for the FPGA board The FPGA board converts the 5V to the 3.3V and 1.8V for the Spartan 7. I added a 3.3V linear regulator (TLV76133DCYR) driven from the 5V switcher to supply the LCD logic and the level shifters. This is a bunch of overkill, but it doesn't add much expense.
The nice thing about the new version of the LCD panel is that it uses LEDs for the backlight running off 12V. The older version required a high voltage inverter.
Unfortunately it changes from a parallel data input to a four channel lvds serial input. I had planned to use the FPGA to drive the lvds signals, but I could not find a cheap FPGA board that allowed the power supplies to the FPGA to be set so that lvds signaling could be used. So instead I an using SN65LVDS1DBVR chips to convert the 3.3V logic from the FPGA to lvds.
I bread-boarded the FPGA and lvds interface and it works fine. I have now made a pcb with all of the circuitry and am working on trying to make it work.
One problem I've found is that I haven't been able to find a PLCC socket that fits down over the RAMDAC chip well enough to make good electrical contact and stay mechanically attached. I have purchased several through-hole and smt versions of the 44 pin PLCC socket and none of them work well. I can see from the photos that Vincent sanded the top of the socket down. That helps some. Also, you have to remove some small standoff posts from the inside of the socket so that the RAMDAC chip fits deeper into the socket. Those changes barely work, but there isn't a really solid fit. I have been working on re-shaping the contacts in the through-hole socket and am able to get what looks like a reasonably good connection.
Another problem I'm having is due to needing a 175MHz clock for the lvds outputs to the lcd. My plan was to use the 25MHz clock to the RAMDAC and use the MMC module in the Spartan 7 to generate a phase locked 175MHz clock. When I tried it on the breadboard, it worked great. But when I try it in the o'scope, the 24MHz clock is too jittery to get a good phase lock. It may be specific to the TDS 524A. The clock distribution on other models is different. I'm able to get a fairly decent display, but there is some noise and jitter in the display that shouldn't be there. If I use the 100Mhz clock on the FPGA board instead, it has a good clean 175MHz signal, but since it isn't synced to the 24MHz pixel clock in the 0'scope, there is some ripple in the display. I'm still trying to come up with a good solution. It wouldn't be an issue if you use the older version of the LCD that doesn't use lvds (if you can still find one). And it may be OK with a different model o'scope. There is something about the clock routing on my o'scope that makes it pick up jitter in the 24MHz clock signal between the oscillator and the RAMDAC.
The vhdl code from Vincent seems to work, although I think the jitter in the clock signal makes it act up every now and then. I think I will be able to tweak it to make it stable with my o'scope, and if yours doesn't have the excessive jitter in the 24MHz clock, it will probably be fine.
Terry
ltarjanyi75:
Hi Terry,
Thanks for the information about your project, it is very valuable, since I'm trying to do the same. :)
I also have a G065VN01 V2, which I could drive by a Spartan 6 devboard. I have not tried to attach it to RAMDAC yet, so you are ahead of me. This jitter issue does not sound promising, but will see what it will be in my case (744A scope). I don't know how, but maybe the HSYNC/VSYNC signals of RAMDAC can be used to provide synchronization on the FPGA.
Regarding FPGA code, Vincent's code is a great help, I more or less understand how it works now, though I have plenty to learn, since it is my first FPGA project.
I also only tried to attach one version of PLCC socket onto the RAMDAC and I agree, that it does not fit correctly. I did not have time to play with it more and to look for other types, because I'm currently focusing on the power board and FPGA board design.
If I'm correct you also plan to build your own FPGA board, which you can directly plug with the socket to the RAMDAC. (And not a ready made FPGA devboard which you fit on a PCB with socket, like Vincent did so far.)
Now I work on the power board, which can be attached to J5 socket of the scope board. It has 5V pins beside the 25V, so you don't need to convert the 12V down to 5V.
Bye,
Laszlo
TerrySt:
Laszlo,
I started out planning to use an FPGA board (S7 mini) (https://shop.trenz-electronic.de/en/TE0890-01-P1C-5-A-S7-Mini-Fully-Open-Source-Module-with-AMD-Spartan-7-7S25-64-Mbit-HyperRAM). but I may try doing an FPGA on my own board. I have been itching to try my hand at some bga soldering.
I'm attaching pictures of what I currently have. I went with a fairly large board because I wanted to use the two nearby support points in addition to the RAMDAC socket. This meant using an extra board for the socket that let me adjust the height to match the supports.
TerrySt:
Back side with the socket board.
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