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Tektronix TDS744 CRT to LCD color converter FPGA module DIY
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TerrySt:
I think the issue I am having with syncing is due to power supply noise or ground bounce on my new board.  I’m still working on it but it looks like the clock jitter is way worse after the level shifters I am using.  Once I fix that, it is easy enough to just use the pll or Mmc module in the Fpga to lock onto the 25 MHz click and generate the 275Mhz clock needed for the lvds signals to the new lcd panel.   

Terry
TerrySt:
I've been working on tracking down the cause of the clock jitter that is causing noise in the display.  Unfortunately, it looks like it is caused by my decision to use the level shifter ICs to convert from the 5V logic levels in the o'scope to the 3.3V signals needed by the FPGA (Spartan 7).  The chip I was using is the 74LCX541D octal non-inverting buffer.  It was a bad idea for a couple of reasons.  First, I completely ignored the fact that the data bus signals get tri-stated.  That leaves the input to the buffer floating, which is a bad idea.  They will draw excessive current and even oscillate.  I could see signs of that and it caused a lot of noise on the power and grounds.  The other reason is the simultaneous switching of several signals on the same chip.  This would probably be OK for most of the signals, but when the clock is fed through the same chip that has seven other signals all switching at the same time, the clock gets noise introduced onto it that causes jitter.
I'm not sure what I'm going to do instead.  I checked the two methods I mentioned earlier (resistor divider on each line or red LED and Schotky diode in parallel on each line.
The resistor divider slows the rise time as expected.  I used 330 Ohms serial and 680 Ohms shunt.  That degrades the rise/fall times, but would probably work OK.  Those values load each signal line by about 5mA.  Lower values would improve the slew rates, but at the expense of extra loading.
The LED/Schottky approach works better. 
Here are o'scope shots of each approach.  Either would probably work.  Maybe I could use the level shifters for most of the signals and use the LED/Schottky for the 8 data bus signals and the clock.

Terry
Tantratron:
Hello Terry,

I do not have knowledge on FPGA for digital video neither do I know well the operation of the RAMDAC. However I'm using two LCD Kit from Simmconn labs so I took pictures of the board and quick voltage measurements which I can share later if you need.

The more I think about what is written in his invoice The Xilinx FPGA design in the NewScope-5/6/7/8/9 kit is released under GPL 2.0 licence, which means that you have written offer to receive the source code of the FPGA design. The source code is available upon request. The schematics, PCB layout and firmware remain proprietary. This seems to only concern the FPGA firmware, the FPGA plug or board and probably not the power plug board.

After all, the power plug is not real brain, just board re-using the +5Vdc and +25Vdc rails from J5 connector then generating via LDO and buck regulator 3.3Vdc and +12Vdc. Note that I happen to have pictures of this power plug version 0 from 2014 which obviously was revised version 1 in 2018 so the power generation or conversion from J5 rails could be not obvious unless he was obliged to redesign due to lack of components. Wether using a LDO or buck regulator, all these schematics and pins out are standard and found in many datasheets.

First thing, his FPGA is SPARTAN XC3S50A and the board has a secondary LDO generating 1.2Vdc from the incoming 3.3Vdc (why 1.2 Vdc is needed, no idea).

Second thing, I recommend from a local EMI and EMC point of view to rather generate the 3.3Vdc from 5Vdc instead from 25Vdc -> 12 Vdc -> 3.3Vdc because deep down conversion can sometimes generate lot of interference depending on the PCB layout. Maybe these are some noise corruption affecting your jitter, no idea but there must be serious reason Simmcon labs used both 5Vdc and 25Vdc from J5 connector.

Last thing, in the initial version, both HSYNC and VSYNC were routed from J5 to FPGA, later revision only routes HSYNC but I'm really not certain this signal is important because the key thing is the 24 MHz quartz near U199 chip (ADV471 RAMDAC) receiving the FPGA plug.

Attached some pictures if they can help anybody, just my 2 cents

Albert


TerrySt:
Albert,
Thanks for the pictures.  Their solution is nice and small.  Very well done.  Mine is much larger since I am using an FPGA dev board instead of an FPGA.  I wanted to use the Spartan 7 and it is only available as BGA.  So at least for my first try, I'm sticking with a dev board so I don't have to solder bga.  I may try to make my own fpga board later.
I don't know why they need to route either hsync or vsync from the J5 connector to the fpga.  I just use the /BLANK signal from the RAMDAC.  It seems to work great.
The socket is interesting.  I purchased what I think is that same socket (Methode p/n 213044601) and it is very difficult to get it to fit over the ramdac and stay in place.  Might work with a very small board like they have but not a larger one like mine.  It would keep popping off.  I've purchased several other brands of socket, and none seem to work well without modification.  The Methode one is probably the best I've tried.

Terry
TerrySt:
I managed to add the red LED and Schottky diode level shifters in place of the I.C. level shifter on the 8 data bus and the clock lines.  The noise issue is gone and the display is nice and clean.   :)
I'll play around with it and see if it is stable while I start working on a re-spin of the board.

Terry
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