EEVblog Electronics Community Forum
Products => Test Equipment => Topic started by: Scratch.HTF on November 15, 2018, 01:00:38 am
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This unit is used for testing TV main boards with an LVDS interface for the LCD, and it has a VGA output which is fixed at 1024x768 60 Hz - when I first connected it, the image was noisy and wavy, but when I properly grounded the LVDS shield, the problem was fixed; pressing the red button selects the data format (most likely for bit depth).
There are two scalers programmed in the FPGA; one for the built-in LCD screen and one for the VGA output.
The digital ICs are:
Xilinx XC6SLX16FTG256 (FPGA - has DeviceDNA but does not offer AES encryption for the configuration - only the largest devices in the Spartan-6 family offer this encryption which can optionally be used)
Winbond 25Q32 (SPI flash for FPGA configuration - also stores configuration changed by the red button)
Samsung K4B1G1646G-BCK0 (64M x 16 x 8 bank DDR3-1600 SDRAM)
GM7123C (330 MHz 10-bit VGA DAC - equivalent to ADV7123)
043056B0-40 V3 (480x272 24-bit parallel RGB LCD)
Additionally, there are three voltage level translators (two differential pairs each) for the LVDS input and the master oscillator is 27 MHz.
A JTAG header (JF1) is also present.
I am looking for someone capable of reprogramming the FPGA so that the VGA output is not scaled down (e.g. a 1920x1080 60 Hz output on VGA with a 1920x1080 60 Hz LVDS input) - reduced or low LCD blanking overheads should also be converted to standard blanking overheads e.g. a 1920x1080 LCD controller with a 138.5 MHz pixel clock and reduced blanking overhead input should be converted to a 148.5 MHz pixel clock with normal blanking overhead for the VGA output; so therefore, known LCD panel resolutions should be programmed with parameters for blanking overhead conversions.
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Attached is technical information and modifications; the panel LVDS interface is limited to around 600 MHz per lane, and I cannot find any functionality on unmounted switch S1.
And from what I see, the LVDS clock can be up to 160 MHz and the pixel input can be either single or dual pixel, depending on the LVDS transmitter and (often panel manufacturer specific) panel receiver IC.
For each pixel input (with separate clocks), 6 bit RGB uses three pairs, 8 bit RGB uses four pairs, 10 bit RGB uses five pairs (and although I have seen provision on an IC in an LG 50PG60UD, 12 bit RGB most likely uses six pairs which would not function correctly with this tester).