EEVblog Electronics Community Forum
Products => Test Equipment => Topic started by: taldarin on May 16, 2015, 02:45:15 pm
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Hello guys,
I am new in this great forum.
I have found here great schematics for Hantek and similar oscilloscopes:
https://www.eevblog.com/forum/testgear/hantek-tekway-dso-hack-get-200mhz-bw-for-free/msg214613/#msg214613 (https://www.eevblog.com/forum/testgear/hantek-tekway-dso-hack-get-200mhz-bw-for-free/msg214613/#msg214613)
made by tinhead user.
Overall the architecture of device is pretty clear for me (at least I think so), but I am not understanding a few parts of it :-//.
1. In front ends they placed 3 stage amplification circuit: FET input buffer, Variable gain diff-amp, diff amp for driving ADC
It's clear that we need VGA in front end but why they use this FET buffer? VGA itself should have pretty high impedance input. Also why we need another buffer after VGA to drive ADC? Even in datasheet of AD8370 we see ADC interfacing (maybe varicap is reason of it) ?
2. In Offset Control circuit they use push-pull buffers e.g. for OFFSET2-CH1 voltage. Why they doing it for just driving VGA input? As I understand simple opamp buffer configuration should work fine.
3. In Offset Control circuit they use just one shift register and one DAC for controlling 9 types of offset voltages. How did they hold offset values of 9 outputs? The outputs can be different values right?
So it will be great if some one helps me to understand this aspects of the design.
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The VGA has a differential input impedance of about 200 ?. The scope has a 1 M? / 30 pF (or so) input impedance. So you need a buffer. A FET buffer.
2. In Offset Control circuit they use push-pull buffers e.g. for OFFSET2-CH1 voltage. Why they doing it for just driving VGA input? As I understand simple opamp buffer configuration should work fine.
The TLV274 is likely not stable with 10+ µF capactive load (while they don't give a number for the output resistance the low output drive ability suggests a high output resistance, which creates a pole with external capacitance and thus leads to phase lag), the additional push-pull buffer lowers the output resistance and thus improves loop stability (by increasing the phase margin). Still it seems they had some issues there, look at the 10 nF compensation...
3. In Offset Control circuit they use just one shift register and one DAC for controlling 9 types of offset voltages. How did they hold offset values of 9 outputs? The outputs can be different values right?
The 100 ? + 6.8 µF are a low pass filter, so if they multiplex the analog inputs fast enough the output voltage will be nearly constant. Although it works, I don't regard this design as very good, since the op amp inputs are essentially open circuit while not selected. A real S/H is IMHO the better solution.
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Thanks a lot dom0 :clap:.
Now I understand that I need be more attentive to details of design.
For 3rd point I was thinking about fast switching technique, but I think that it is not good enough to use in this kind of device.