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Upgrading DSLogic Basic to Plus without EEPROM modification
thm_w:
--- Quote from: masterx81 on April 01, 2020, 06:08:32 pm ---Sorry but what's the difference between the two type of leads? Less noise at high frequency?
--- End quote ---
Yeah shielding could help a bit with noise. Bandwidth should be higher with the coax. But no one has actually compared the two.
masterx81:
I have one of the "older" leads, but also this seem a really small coax cable, connected to ground on the unit side
RoGeorge:
Any cable is also a transmission line. In a transmission line, when the impedance is not matched, the signal is reflected back and forth, making one see spikes or ringing on the signal edges if it is observed with an oscilloscope, or fake/multiple edges instead of only the correct edge when looking with a signal analyzer that can see only zeroes and ones.
Note that this reflections happens no matter how low is the frequency of the signal. What matters most in case of digital circuits is the raising and falling time of the edges. The fastest the edge, the more problems, no matter if we look at a 100 Hz or a 100 MHz signal.
TL;DR
The shielded cable is supposed to:
- have a controlled impedance, so one can match the impedance, and thus observe the correct signals and correct edges, not influenced by signal reflections.
- have a controlled velocity factor (and thus an equal propagation delay for all wires), so the edges from many parallel lines are observed in the correct order.
With normal (unshielded) wires, the impedance varies wildly, depending how the wire is bent or twisted, or how close is relative to other wires, or relative to GND.
This video from w2aew explains very well the idea of transmission lines and reflections, and also shows the waveform produced by the combination between the original signal and its reflections. Keep in mind that the same phenomena happens at any frequency, no matter if it's sinusoidal signal for a radio transmitter, or square signal for a digital circuit. The signal analyzer will be very confused by the strange waveforms appearing because of reflections. Also, keep in mind that those reflections seen in the video are nice and stable only because the pulses duration is constant. With varying digital signals, the combination between original and reflected signal can turn even the cleanest waveform into an unrecognizable mess. So, here is why, and how it looks like for the most simple cases:
Now, how worry should we be? For looking at signals on an Arduino or a breadboard, using short wires like the ones coming with the probes, most probably there will be no visible difference between a shielded cable and a normal wire.
For looking at high speed signals with very aggressive edges, on a PCB with controlled impedance traces, the shielded cable and correct impedance matching is a must.
As an example, if you put a clean square wave (no matter the frequency, but with very fast edges), and don't care about the impedance matching, you can easily see 2-3 fake edges instead of one, especially at maximum acquisition speed.
By fake edge, I mean a few very close transition instead of a single clean falling or clean raising edge. Looks similar with a debounce noise, but it is caused by signal reflections, not by imperfect mechanical contacts.
As a fun exercise, you can see how the number and the distance between the oscillations of a fake edge varies with the length of the connection wire, or with the impedance mismatch. ;D
rfdes:
--- Quote from: masterx81 on March 29, 2020, 09:27:52 am ---Look here for u2b;
https://www.google.com/amp/s/m.habr.com/ru/amp/post/483496/
I've used a thin enameled wire to connect the missing addressing pin. The i've done the eeprom mod and it works perfectly
--- End quote ---
My effort to upgrade my U2 Basic to Plus went poorly. Unless this is not understood, the FPGA pin that drives the A12 Ram pin is connected to GND on the U2Basic PCB. The above link shows that this pin needs to be isolated by carefully 'lifting' the pin from the GND pad. I struggled but managed to get this pin lifted and made the connection to the RAM A12 input. However, the mod failed. I believe that I may have damaged this FPGA pin by updating the EEprom to PLUS and applying power to the board 'before' I isolated the FPGA pin from GND. My belief is that with the board configured as a PLUS version, this forced the FPGA pin to an OUTPUT while it was connected to GND, causing a short circuit and damaging this FPGA pin. I have no proof of this but I recommend isolating the FPGA pin before configuring EEprom to the PLUS version. At this point when I perform an internal test, the test shows all 0 on each line.
Does anyone have any further information regarding this? Curious if others had similar failures.
Take care -
rfdes
thm_w:
The pin should be not connected on both sides, then you add a jumper wire to connect fpga to ram.
It shouldn't be grounded. But I can't remember actually measuring to confirm that.
You can see my photo above: https://www.eevblog.com/forum/testgear/upgrading-dslogic-basic-to-plus-without-eeprom-modification/msg2921384/#msg2921384
Internal test worked OK.
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