Products > Test Equipment
Upgrading DSLogic Basic to Plus without EEPROM modification
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rfdes:

--- Quote from: thm_w on May 15, 2020, 08:50:36 pm ---The pin should be not connected on both sides, then you add a jumper wire to connect fpga to ram.
It shouldn't be grounded. But I can't remember actually measuring to confirm that.

You can see my photo above: https://www.eevblog.com/forum/testgear/upgrading-dslogic-basic-to-plus-without-eeprom-modification/msg2921384/#msg2921384

Internal test worked OK.

--- End quote ---

I've seen the bare PCB without the FPGA installed and the I/O pin used to drive A12 is definitely grounded.  My issue was resolved due to an intermittent solder bridge on the FPGA between two signals used to read/write to the RAM chip.  These two pins are located about 10 pins away from the i/o signal used to drive A12.  It was just a coincidence that this started giving me trouble at the time I was implementing the upgrade modification.  Just my luck.  Anyway after clearing the bridge all is well.
take care -
thm_w:

--- Quote from: rfdes on May 15, 2020, 10:45:54 pm ---I've seen the bare PCB without the FPGA installed and the I/O pin used to drive A12 is definitely grounded.  My issue was resolved due to an intermittent solder bridge on the FPGA between two signals used to read/write to the RAM chip.  These two pins are located about 10 pins away from the i/o signal used to drive A12.  It was just a coincidence that this started giving me trouble at the time I was implementing the upgrade modification.  Just my luck.  Anyway after clearing the bridge all is well.
take care -

--- End quote ---

Thank you for noticing :-+, took it apart again and it was grounded as you say. Have to lift the pin using a pointy exacto knife.

From what you are saying self-test should indicate failures in memory, but maybe I wasn't looking closely or its not fully testing the memory capacity, as I don't remember seeing anything unusual there.
robca:
Has anyone found a good source to buy just the shielded cables like the Plus uses? I'm upgrading my U2Basic (thanks to everyone who contributed to this thread) and the only source seems to be https://www.aliexpress.com/item/32999482818.html, for around $30 shipped to the USA

Not sure if it's worth the extra cost, though, so I'll start with the memory upgrade only (and using fx2lafw_eeprom_loader to change the device ID) and see if it works well enough for me at the relatively low speeds I'm likely to use
webhdx:
Here are some remarks regarding upgrade from U2B to Plus. A lot of this information was spread across multiple posts and I wasted some time troubleshooting the issues. So here we go:

1. You need MT48LC16M16A2P-6A, apparently -6A is very important.
2. Replace RAM chip with the new one.
3. You have to lift the leg on FPGA! The leg is grounded by default, it won't work without lifting it. Be very careful, it's extremely easy to break the leg off.
4. Solder a wire between unconnected legs of FPGA and RAM. There are pictures in the topic so you can easily count which legs you have to solder to. Just remember you also have to left the pin on the FPGA!
4. Solder a wire across leg 4 and 7 of the EEPROM chip. You can also short it with tweezers for the programming but it won't do any harm if you leave the wire in place.
5. Use fx2lafw_eeprom_loader.exe software to program new firmware. You will find the link here in the topic.
6. Now the thing I had most problems with - there are a lot of firmware files being posted. I don't know why others had good luck with them but in my case a lot of them wouldn't work. The program would reports invalid characters in the hex file. So what worked 100% for me was:
fx2lafw_eeprom_loader.exe -t M24128 -p DsLogicPro

The firmware DsLogicPro should be provided with the software (ref. https://github.com/podonoghue/LogicAnalyser/blob/master/Software/fx2lafw_eeprom_loader/bin/DsLogicPro). You don't have to look for any special firmware files here in the topic.

Steps above converted my U2B to Plus version which happens to work in all DSView versions on macOS. People had issues with newest releases or they had to replace bitstreams but none of that was required for me. I use DSView 1.12 which is the newest available version at the time of writing this post. Also RLE seems to work quite reliably for me, even at 400MHz. Not sure if the person having issues did the wiring properly by matching length of the wire (should be 38.5mm). I used 0.1mm enameled wire which is probably the best for the job. With RLE you won't capture over ~400ms in buffered mode, not sure why you have options for 1, 2 or even 10 seconds.

DSView is a piece of shit and I prefer PulseView (mainly because I can use my own decoders) which works with DSLogic Plus but not with U2B.
robca:
I recently updated as well, and I was planning to summarize the new steps, but you beat me to it :) well done!

Couple of notes:


* Lifting the FPGA pin is, by far, the most challenging part of the upgrade. The rest, especially if using bismuth or ChipQuik to remove the RAM is trivial. The FPGA pin requires a good soldering iron, good eyes or a microscope, and 3 hands  ::). And even so you risk bridging the neighboring pins or breaking the pin off. Do this only if you have previous experience with similar tasks, or practice on a dead board first. Corollary: if your time is worth anything, you are better off buying the Plus version directly

* The instructions are mostly written for the upgrade from Basic to Plus, not from U2B which is the one sold now. You cannot edit the file extracted from the U2B and modify only 2 bytes. The binary file is different. You need to find a Plus firmware binary. I downloaded the one described here https://habr.com/ru/post/483496/ (use Google translate), and uploaded on github https://github.com/User420t/DSL (the password is in the post with all the steps... now sure why it was password protected)

* If you use Windows, you need https://github.com/podonoghue/LogicAnalyser/tree/master/Software/fx2lafw_eeprom_loader/bin
@webhdx as far as I can tell, the DsLogicPro.bin file (at least in my distribution) is 334k. The EEPROM is only 16k. The file I used, 24c128_plus.bin is 16k. If you use the hex version (same content, different encoding), it's 46K. 334k is way too big. How did you manage to make it work? The *.bin files in the DsView distribution are, as far as I can tell, hdl files for the FPGA, and what it's stored in the EEPROM is just the firmware for the Cypress USB interface and to tell the system what type of board you have. The hdl is then uploaded by either DsView or PulseView, the correct version for the type of device used (Basic, U2B or Plus). It looks as if DsLogic used the Pro moniker at one point, but now it's probably the Plus version

DsLogic uses different hdl (DsLogicPlus.bin, DsLogicBasic.bin, DsLogicU2Basic.bin, etc) depending on the ID of the board. The board we bought has a Cypress firmware in EEPROM that identifies it as a U2Basic, so needs one version of the hdl (the one that knows some pins are tied to ground and using a smaller RAM). After the modification, we need to update the EEPROM to tell the system we now have a different board, with more RAM and identical to a Plus. Then DsView/PulseView will upload the correct hdl and use all the memory, plus unlock the faster data capture rates. Quite understandably, DsLogic doesn't expect the users to change the EEPROM, so they do not provide the right firmware in the distribution. And we need someone with an actual Plus to dump their EEPROM and share the bin file

Also, DsView *is* PulseView with a different UI and a few functionality changes. As a matter of fact, there were a lot of tensions between the sigrok community and DsLogic because DsLogic did not properly attribute the code nor posted the changes. You can use any PulseView decoder in DsView just by copying them in the right directory. The current released version of DsView lacks a lot of decoders, but all the decoders have been checked into their github repository (from PulseView) and can be used
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