Products > Test Equipment

Upgrading DSLogic Basic to Plus without EEPROM modification

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mwb1100:
I don't know exactly how helpful this might be:  I believe support for the Pango was added in this commit to DSLogic's github (https://github.com/DreamSourceLab/DSView.git):


--- Code: ---C:\devtrees\DSView>git bugnote 2532ad4c1
```
in repository: C:/devtrees/DSView
in branches:  master
============
commit 2532ad4c
Author: dreamsourcelabTAI <tzz@dreamsourcelab.com>
Date:   Mon Dec 12 15:58:05 2022 +0800

    Suports new hardware

A       DSView/res/DSLogicPlus-pgl12.bin
A       DSView/res/DSLogicU2Basic-pgl12.bin
M       libsigrok4DSL/hardware/DSL/command.h
M       libsigrok4DSL/hardware/DSL/dsl.c
M       libsigrok4DSL/hardware/DSL/dsl.h
============
```

--- End code ---

And in case it helps, the Pango firmware files have been updated in these commits:


--- Code: ---C:\devtrees\DSView>git ls -- DSView/res/DSLogic*-pgl12.bin
264e7c46 DreamSourc.. 2023-06-27  update FPGA bin files (version E)
b9b143c3 DreamSourc.. 2023-06-16  update fpga bin file for DSLogic
63955d72 dreamsourc.. 2023-04-26  Loop mode
cfa0c1cb dreamsourc.. 2023-01-12  update: new firmware file
2532ad4c dreamsourc.. 2022-12-11  Suports new hardware

--- End code ---

robca:

--- Quote from: mwb1100 on March 05, 2024, 09:52:52 pm ---I don't know exactly how helpful this might be:  I believe support for the Pango was added in this commit to DSLogic's github (https://github.com/DreamSourceLab/DSView.git):


--- Code: ---C:\devtrees\DSView>git bugnote 2532ad4c1
```
in repository: C:/devtrees/DSView
in branches:  master
============
commit 2532ad4c
Author: dreamsourcelabTAI <tzz@dreamsourcelab.com>
Date:   Mon Dec 12 15:58:05 2022 +0800

    Suports new hardware

A       DSView/res/DSLogicPlus-pgl12.bin
A       DSView/res/DSLogicU2Basic-pgl12.bin
M       libsigrok4DSL/hardware/DSL/command.h
M       libsigrok4DSL/hardware/DSL/dsl.c
M       libsigrok4DSL/hardware/DSL/dsl.h
============
```

--- End code ---

And in case it helps, the Pango firmware files have been updated in these commits:


--- Code: ---C:\devtrees\DSView>git ls -- DSView/res/DSLogic*-pgl12.bin
264e7c46 DreamSourc.. 2023-06-27  update FPGA bin files (version E)
b9b143c3 DreamSourc.. 2023-06-16  update fpga bin file for DSLogic
63955d72 dreamsourc.. 2023-04-26  Loop mode
cfa0c1cb dreamsourc.. 2023-01-12  update: new firmware file
2532ad4c dreamsourc.. 2022-12-11  Suports new hardware

--- End code ---

--- End quote ---
Could still be possible, but one needs to EEPROM values for the new U2Basic and Plus. The right ID is needed so that DsView can decide to send the new bitstream instead of the old.

From the picture, it seems that the line A12 is connected in the memory chip (pin 36). If so, that means that the hardest part (lift the FPGA pin to add the address wire/pin) is not needed on this new device. A low risk test should be possible: rename the FPGA bitstream for the new Plus bitstream as the U2Basic (so that DsView sends the Plus bitstream thinking it's sending the U2Basic), capture data to fill the memory of the Plus, and monitor the A12 line. If there is activity in the A12 line, it might be possible to perform the hack by replacing the memory and finding the right ID for the EEPROM (by asking a new Plus user to read their EEPROM, which can be done without opening or any risk to their device)

If A12 is tied to ground like it was in the Spartan U2Basic, the hack is probably too hard...

Pandor:
Just wanted to share another success story.
Thanks to all who contributed to the cause.

profrook:

--- Quote from: robca on March 05, 2024, 10:40:56 pm ---Could still be possible, but one needs to EEPROM values for the new U2Basic and Plus. The right ID is needed so that DsView can decide to send the new bitstream instead of the old.

From the picture, it seems that the line A12 is connected in the memory chip (pin 36). If so, that means that the hardest part (lift the FPGA pin to add the address wire/pin) is not needed on this new device. A low risk test should be possible: rename the FPGA bitstream for the new Plus bitstream as the U2Basic (so that DsView sends the Plus bitstream thinking it's sending the U2Basic), capture data to fill the memory of the Plus, and monitor the A12 line. If there is activity in the A12 line, it might be possible to perform the hack by replacing the memory and finding the right ID for the EEPROM (by asking a new Plus user to read their EEPROM, which can be done without opening or any risk to their device)

If A12 is tied to ground like it was in the Spartan U2Basic, the hack is probably too hard...

--- End quote ---

Just got mine U2Basic today, with PGL12G FPGA.
The USB device ID is in the commit.


--- Code: ---    {0x2A0E, 0x0030, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic PLus", NULL,

--- End code ---


--- Code: ---    {0x2A0E, 0x0031, LIBUSB_SPEED_HIGH, "DreamSourceLab", "DSLogic U2Basic", NULL,

--- End code ---

Btw, anyone found anything on they new FPGAs?

ahmad_k:
Can anyone dump the new Pango Plus EEPROM content ? I got my u2basic version along side with winbond memory, but i want to flash the EEPROM with correct firmware. Editing VID and PID only will not make the device works

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