Products > Test Equipment
USB logic analyzer - what's the current "favorite" for ~150$? Hantek 4032L?
TK:
If you need state mode sampling (match signal that changes based on a fixed clock) you need to use the external clock input. The logic analyzer will sample at every clock edge (rise or fall). If you are sampling in timing mode, you are going to repeat a certain state and miss others. It is not going to capture perfectly every single clock edge rise or/and fall.
wpwrak:
--- Quote from: abraxa on July 05, 2018, 09:25:43 pm ---Not even a single line of usable code because they not only didn't want to work with us, they actively sabotaged any effort of upstreaming anything.
--- End quote ---
Hmm, if they made derivative works of code that was distributed to them under the GPL, and refuse to make their changes available, then you may want to have a chat with the FSF/FSFE. Companies that thought they could get away with disregarding the GPL have been taken to court, and lost. See also https://en.wikipedia.org/wiki/Gpl-violations.org
Of course, if you're talking about code that isn't a derivative work, or if the original was licensed under different terms, then the situation would be different.
- Werner
wpwrak:
--- Quote from: abyrvalg on July 17, 2018, 02:56:12 pm ---A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal.
--- End quote ---
A more accurate test would be to gate the signal to have an exactly known number of cycles. Then you can just trigger on the first edge, grab the sequence, check that the recording isn't cut off, have the cycles counted, and see if the numbers match. If you can use a PLL as clock source, you can also vary the frequency to see when exactly things get interesting.
- Werner
abyrvalg:
Oops, I didn’t posted the really important numbers: the edge count remained stable over ~10 attempts with DSLogic, but with 4032L there were deviations by more than 100 edges sometimes. Anyway, I’m planning to test it with a clock+counter signals in state mode later.
DSLogic code is open and being updated regularly, it’s just refactored in a way hindering automated merging - not a license violation formally, but looks a bit unfair to the original project.
toli:
Just a small update, the DSlogic Plus has arrived here very quickly. Its much lighter than I've expected, but seems quite well made. The shielded leads are very nice, even if a bit too stiff. The hooks (as always) are of rather low quality, I will have to look for something nicer to get.
One thing I didn't like in v0.99 of DSview is the change from sample length to sample time. While it makes more sense in many cases, for some of my use cases it would have been better to have it as it was in older version. I hope they will allow users to select which they want to see in the next version.
edit:
seems like the second issue was a misunderstanding and not a bug. Post has been revised.
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