USB logic analyzer - what's the current "favorite" for ~150$? Hantek 4032L?

[toli]

Hi All,

I was looking into possibly extending the capabilities of my gear when it comes to a logic analyzer. Since this will eventually be used mainly for hobby use, I'd like to keep it at ~150$ or less.

My "must haves" include 16 channels, samples rate of >100MSPS, and adjustable threshold level (some of the things I use don't have "standard" logic levels), a couple Mpoints of memory are also very much appreciated.
If I'm being picky, I would actually like to get >200MSPS sample rate, more than 16 channels, and it would make my life easier for some use cases to be able to use external clock for sampling.
I will use it mostly as a general purpose device for SPI/I2C/RS232/similar simple interfaces I might use in projects.
However, having a more capable device will allow me to use it for reading data out of test chips I'm working on as part of my Ph.D. studies. While I do have tools to do this at the university, having a small device at home that can allow me to work on this whenever I want is a great advantage.

One candidate I'm currently looking at is the Hantek 4032L. Its almost within budget, it has 32channel, 64Mpoints per channel, 400MSPS, adjustable voltage levels, and supports (in latest fw) external clock for sampling. From what I read the software is ok at best, but it seems to be well supported (and improving over time) by PulseView which is a great point in its favor (I could perhaps implement additional decoding here instead of MATLAB like I'm doing today).

After this long intro, about time I get to the questions
1 - I've seen limited number of user reviews of the 4032L, and the few I've seen are from a few years ago. Are there any users of this device here on the forum that can share their experience with the device/provide real world opinion about it? Is it any good? Are there any major bugs/limitations? Anything else I should be aware of before getting one?
2 - Are there other suggested devices that are considered better/will fit my needs better?

Thank you.

[maginnovision]

If you don't need the 32 channels I'd say get something with better support. If you do want to get the 4032 you need to use sigrok or write your own program for anything other than basic decoding. I'm torn on sigrok, it's missing alot of things I need but the 4032 developer is doing what he can with the driver. The factory software is sufficient for individual lines or parallel busses. The advanced triggers are the reason I still use it. The software is pretty much unusable in 4K though. Overall, I'd say it's good but first and third party software have their issues. If you have any specific questions I can try to answer them.

[TK]

You can check the Zeroplus LAP-C 16032... it has only 16 channels, 100MSa/s and 32K per channel but it supports over 100 protocols included for free.  Price in the US is around $130

[1anX]

I got the DSLogic Plus and it does what I want!        http://www.dreamsourcelab.com/order.html
Check the thread on this forum.

[toli]

Thank you all for the comments.

maginnovision, assuming I will be using sigrok, what are the issues you are seeing with this combo? From what I read the current version supports external clock, and has most of the features implemented already, or am I wrong? Where do you feel it falls short compared to other options?
One more thing has to do with operating it on an external clock. Any idea how fast this clock can actually be? I see this mode is much slower for most devices, but I can't see a note of this mode in the spec for the Hantek.

TK, 32KB is just not enough for me unfortunately. There are some cases where I need a few MB. 100Msa/s are also the bare minimum I can get away with for some applications. So if I can get stronger HW for the price I will definitely go that way.

1anX, from what I read about it, the SW is based on sigrok too, and therefore has many similarities. If that is the case, will it actually be any better than using sigrok on the 4032L? The reason I'm asking is because when comparing the spec, its a stronger unit (the Hantek). More channels, higher sample rate, and more memory. For instance, I now have a project where the output is 12bit parallel bus (actually 32, but I can get away with 12 at a time) + 50MHz sample clock. For this the DSlogic is running at the edge of what it can do, although it does seem to support this. For this I has to implement the readout using a Cypress FX3 EVB. While it wasn't too bad, if I could simply hook it up to a LA and dump a few MB's per channel into a csv file - it would have been even faster and easier.

[maginnovision]

maginnovision, assuming I will be using sigrok, what are the issues you are seeing with this combo? From what I read the current version supports external clock, and has most of the features implemented already, or am I wrong? Where do you feel it falls short compared to other options?
One more thing has to do with operating it on an external clock. Any idea how fast this clock can actually be? I see this mode is much slower for most devices, but I can't see a note of this mode in the spec for the Hantek.

Sigrok doesn't support advanced triggers, it's high or low for one line only. If that isn't the case then for me it crashes 100% of the time otherwise. That includes if I forget to deselect one line as trigger before selecting another, I don't need to start an acquisition. The external clock is most useful only if you can match your clock rate to the sample rate pulldown selection. Although potentially useful as well for capturing a lot of serial data. Again it may just be me but it crashes when using decoders and trying to scan through the data before they're fully decoded. With 64M samples that can take a while though. It doesn't save the setup on restart/crash, so if you have line A13 following A15 once it restarts it resorts back to numerical order. If you start sigrok before the LA is connnected and powered on you again lose your entire setup including labels and added decoders. The one saving grace there is typically when you re-add the decoders the lines are still set but you still lose your labels. Even without decoders if I try to scan through data during an acquisition or shortly after it crashes. It's alot of little things that make it hard for me personally to recommend it but when their software also has an equal number of issues... I end up keeping both installed. Neither of them can take full advantage of the hardware.

The good news though is that sigrok probably will improve. The hantek software never will.

[toli]

Thank you for the detailed response, highly appreciated.
The problems you describe sound like a major PITA, and if this is indeed the current situation I'd like to avoid it.

The external clock is most useful only if you can match your clock rate to the sample rate pulldown selection.

I think this is only true if you want a time stamp on the data. For my usage of external clock I don't care about time stamp, only about being able to maximize the sampled data. Oversampling (with high speed internal clock) is a waste of memory if I can instead sample only when valid data is present

I was under the impression sigrok now works well with the Hantek device, and will just keep on improving. However, what you are describing is barely usable (if I understand correctly), and there is obviously no guarantee this will improve in the foreseeable future 

Are these issues shared among all users of this device, or is this something that you only observe on one machine/operating system/other combo? Just trying to understand if this is something that can circumvented somehow.

[abraxa]

If that isn't the case then for me it crashes 100% of the time otherwise. That includes if I forget to deselect one line as trigger before selecting another, I don't need to start an acquisition. The external clock is most useful only if you can match your clock rate to the sample rate pulldown selection. Although potentially useful as well for capturing a lot of serial data. Again it may just be me but it crashes when using decoders and trying to scan through the data before they're fully decoded. With 64M samples that can take a while though. It doesn't save the setup on restart/crash, so if you have line A13 following A15 once it restarts it resorts back to numerical order. If you start sigrok before the LA is connnected and powered on you again lose your entire setup including labels and added decoders. The one saving grace there is typically when you re-add the decoders the lines are still set but you still lose your labels. Even without decoders if I try to scan through data during an acquisition or shortly after it crashes.

While I appreciate your honest criticism, I would like to point out that no problems will ever be fixed that the team doesn't know about. PulseView works just fine for a whole lot of people, and when something doesn't work for you, it's worth creating a bug report in bugzilla.

[toli]

abraxa, can you share your input about the combo of 4032L with sigrok?
Getting more info from as many users as I can will be very helpful in making the right decision here.

I understand sigrok is the work of people from the community, many of which are members of this forum (and perhaps it the opportunity to thank them for the work they are doing  ). As such, I understand it will improve over time which is a great benefit of such software. I just want to understand where its at right now, and what is expected in the near future so I'll know if this combo will be useful for me now or I should looks for another piece of HW (be it with sigrok or other SW)

[coppice]

While I appreciate your honest criticism, I would like to point out that no problems will ever be fixed that the team doesn't know about. PulseView works just fine for a whole lot of people, and when something doesn't work for you, it's worth creating a bug report in bugzilla.

I think Sigrok suffers a lot from people giving it a try, finding issues, and moving on without taking any further action. That's death for an open source project, while rational feedback is its life blood.

[Doctorandus_P]

If you have any curiousity in te direction of Sigrok I would recommend to start with a "8ch 24M" box from Ali / Ebay. The price of this box is so low (About EUR 5) that there is no reason not to buy it, even though it does not live up to your full specs.
I've captured and decoded some low-speed USB signals (1.5mbit/s) with this box and it  is enough to give you an Idea of what Sigrok can do.

A general CY7C68013A development board goes upto 16 channels in Sigrok, but does not have any input protection. You could add a buffer yourself with the any logic level you like.
You may even state that the input protection is included in the pricetag. Just buy 10 of these EUR3.05 boards, and exchange them if you did something stupid and blew the inputs.

For more capable hardware you may want to have a look at what is supported by Sigrok:
https://sigrok.org/wiki/Supported_hardware

[toli]

Thank you for the comment.
That is exactly what I did, the 4032L is in the supported devices list and seems like the most capable device there
Only problem is that "supported" is a wide term, so I'd like to get more real world comments from users of this combo.

[17_29bis]

One more vote for DSLogic Plus, it was around 130USD, supports up to 400Mhz for 4 channels (see the screenshots for choosing different speed), up to 4G (RLE compression) memory size (256Mb RAM onboard), adjustable threshold level, possibility to use external clock (did not try), long list of decoders (I am familiar with 5 or 6 different decoders), ability to stack them (useful for work with low speed USB devices, fox example), ability to write your own encoders (python), cursor measurements, buffering and streaming data acquisition modes  (USB2 speed limit). It has external trigger input and output (I had a problem with one of them, dont remember which but I still was able to chain Analog Discovery (it has very advanced triggering system) and DSLogic Plus through external trigger connection).

Bad things: the GUI (sigrok fork/ or "being inspired by sigrok") DSView v0.9.7.1 (2 or so years old) was the last public release (but I still prefer ti very much to the original sigrok GUI). The support forum is almost dead, I had a difficult time to setup an advanced trigger but found a work around through the usage of external trigger.

Full specification of the device (less than I paid  ):
https://www.ebay.com/itm/New-DSLogic-Plus-DSLogic-Pro-16CH-100MHz-USB-Logic-Analyzer-/253587496006

Device review:
https://hackaday.com/2017/08/24/dslogic-plus-teardown-and-review/

[toli]

Thank you all for the help so far.
Following the input from members in this thread, as well as more reading over the web since I've started this topic, seems like the current state is the following:
DSlogic Pro - doesn't meet my desired requirements, but does meet my minimum requirements.
HW wise it has adjustable threshold and sufficient memory which are meeting my desired numbers. The number of channels and sample rate and BW are marginal for some of my needs. The external clock seems to be at constant 3.3V level which isn't what I need and I'll have to "fix" it externally with a level shifter.
SW wise it seems like many people aren't too happy with it. This is at least what I read on different forums online, including here, and looking at reviews on websites selling this device.
So overall it will do most of what I need, but for some of the more demanding applications I will have to look elsewhere. The price of <100USD is obviously a nice point in its favor, as well as the slick design of the unit.

However, before I'm settling for something that doesn't really meet my desired needs, I'd like to give that 4032L one more chance. The HW benefits of extra memory (which I don't need, the DSlogic has enough memory for me), and more importantly higher sample rate and BW, more channels, and if I understand correctly adjustable threshold on external clocks - are all very tempting. The fact its almost double the price is something I can live with, its worth the extra cost if it'll save me the drive to the lab at the university by letting me work on my test boards from home.
There is still an open issue about the HW, namely the maximum clock frequency for CLKA/CLKB inputs. I'm still not able to find a straight answer to that question, is it the 150MHz claimed BW, or lower? I have no idea at the moment. I've sent Hantek an email today, lets see if they ever get back to me
The biggest issue I see so far is the SW. I've read maginnovision's comments here, and they are definitely not positive. Despite this, I'm still trying to get input from other users of the 4032L/sigrok combo, to try and get a better feeling of how usable/unusable it really is.

Thank you all again.

[abraxa]

I apologize in advance for hijacking this thread for my comments but I just can't stay quiet.

One more vote for DSLogic Plus, it was around 130USD

Of which exactly $0 went towards sigrok, by the way. Not even a single line of usable code because they not only didn't want to work with us, they actively sabotaged any effort of upstreaming anything.

long list of decoders (I am familiar with 5 or 6 different decoders), ability to stack them (useful for work with low speed USB devices, fox example), ability to write your own encoders (python), cursor measurements, buffering and streaming data acquisition modes  (USB2 speed limit)

...which are all features that the sigrok team (and community, in the case of protocol decoders) is responsible for - including the Cypress FX2 firmware that the DSLogic uses.

Bad things: the GUI (sigrok fork/ or "being inspired by sigrok") DSView v0.9.7.1 (2 or so years old) was the last public release (but I still prefer ti very much to the original sigrok GUI).

Seriously? You applaud them for taking our work, making the UI look "fancy", making money off of it of which we see exactly zero, adding some minor features here and there and then crap on us for having neither the man power nor the time to do the same? Hint: none of us gets paid and we support a wide range of devices - not just one. Making things work for one device is easy, making stuff work for *all* devices is not.

That is exactly what I did, the 4032L is in the supported devices list and seems like the most capable device there
Only problem is that "supported" is a wide term, so I'd like to get more real world comments from users of this combo.

That's in flux, as is to be expected. From the driver perspective, the functionality that you require is implemented. If you look at the driver source, you can see that the threshold levels are adjustable and the external clock can be used. I don't know the device well enough to say whether the threshold levels also apply to the external clocks but I'd assume so. If you want to be sure, you can mail the person who implemented support for external clocks in the driver: https://sigrok.org/gitweb/?p=libsigrok.git;a=commit;h=f49065c6682b720800e05e8e2821a193b251d65a

Regarding the external clock rate: the hardware and driver have no way of finding out what the clock rate is or if it's even stable. That's why you as a user must provide the clock rate using the drop-down menu if you want to have accurate timing information. The fact that there are only pre-defined values can be an issue here I reckon, but that'll be fixed in the future so that you will be able to enter arbitrary values.

[toli]

Thank you for this comment. Regarding external clock, I have no need to know exactly what it is in the software time stamps, as long as I can export all the data to CSV and process it in MATLAB. The question there was about the clock frequency the HW can support - I can't find a straight answer in the device datasheet about the maximum clock frequency I can use in this mode, this will probably be limited by the speed of the IO buffers and comparator they use. I'd guess 150MHz BW as they claim should support 150MHz clock, but one can never be sure unless its in the datasheet or someone else can test it

[maginnovision]

Thank you for this comment. Regarding external clock, I have no need to know exactly what it is in the software time stamps, as long as I can export all the data to CSV and process it in MATLAB. The question there was about the clock frequency the HW can support - I can't find a straight answer in the device datasheet about the maximum clock frequency I can use in this mode, this will probably be limited by the speed of the IO buffers and comparator they use. I'd guess 150MHz BW as they claim should support 150MHz clock, but one can never be sure unless its in the datasheet or someone else can test it

I would expect 150mhz to be the limit. If you just need to export data I suspect using the sigrok CLI should work for you in which case I'd say go for it.

[17_29bis]

Of which exactly $0 went towards sigrok, by the way. Not even a single line of usable code because they not only didn't want to work with us, they actively sabotaged any effort of upstreaming anything.
...which are all features that the sigrok team (and community, in the case of protocol decoders) is responsible for - including the Cypress FX2 firmware that the DSLogic uses.
Seriously? You applaud them for taking our work, making the UI look "fancy", making money off of it of which we see exactly zero, adding some minor features here and there and then crap on us for having neither the man power nor the time to do the same? Hint: none of us gets paid and we support a wide range of devices - not just one. Making things work for one device is easy, making stuff work for *all* devices is not.

All this is very strange. I am the END USER who found DSLogic on the web, checked the specs and bought the device before I  even heard the name sigrok. "0$ dollars, you applaud" - what are you talking about?  And what is even more what am I supposed to do now? Throw it way, ask for refund, start drinking heavily due to the guilt? if you have a problem with dev. of DSLogic then deal with them in civilized way withing drawing the people who has nothing to do with that into it.

[1anX]

DSLogic Plus which is what I purchased and it seems is under your consideration has just released an updated version of their software (based originally on Sigrok as others have pointed out). The software I have been using was V0.98 and I have just downloaded the update V0.99 this week and will install sometime soon.

I like their software, (DSLogic) and have zero problems in using it. My previous experience with Sigrok software and Win 10 and Linux was frustrating to say the least so by using DSLogic's program I was up and running immediately.

Download latest V0.99 here >   http://www.dreamsourcelab.com/download.html

[SMB784]

So I bought the $60 Chinese knockoff of the DSLogic basic, soldered in a $3 sdram chip onto the unpopulated SDRAM slot on the board (creating the equivalent of a $100 DSLogic Plus knockoff), and installed sigrok pulseview on my Raspberry Pi 3B+. The specs on the DSLogic Plus are 400 MS/s sample rate, 256MByte capture memory, and claimed 50 MHz bandwidth, though I suspect that it is much higher, maybe as much as 150 MHz judging by the sample rate

When you build it from the source according to the website instructions, pulseview works flawlessly with this device. Bang for buck, the aforementioned setup beats the pants off of the Hantek, and can handle almost anything you throw at it.

A couple years back i was an extreme sigrok skeptic, but they have worked hard and have released enough updates that I am really very pleased with sigrok, it's great software and you can't beat free

[toli]

SMB784, this device is not meeting my desired spec as I've described above. The 50MHz limitation isn't a function of sample rate for most devices, its about the speed of the comparator and timing constraints of the digital logic. Therefore its impossible to look at the maximum sample rate and understand what the maximum frequency it can sample will be. As I mentioned above, this model (the pro) is my plan B (or maybe C), since it isn't what I really want in a LA. Bang for bug isn't the parameter I'm looking for, I'm looking for something that can technically do what I want, which out of the devices I've seen so far only the Hantek can.
If I come to the conclusion I can't use the Hantek due to software limitation I'll get the DSlogic Pro, and live with the fact it can only due the more basic things I need. But so far it seems the Hantek isn't "dead" yet. Especially considering the SW will keep improving.

I'm still on the fence here though, the two users who have experience with this combo (abraxa and maginnovision) agreeing that it can do what I want, but if I understand correctly there are bugs at the moment that might make it a not so pleasant experience

[SMB784]

SMB784, this device is not meeting my desired spec as I've described above. The 50MHz limitation isn't a function of sample rate for most devices, its about the speed of the comparator and timing constraints of the digital logic. Therefore its impossible to look at the maximum sample rate and understand what the maximum frequency it can sample will be. As I mentioned above, this model (the pro) is my plan B (or maybe C), since it isn't what I really want in a LA. Bang for bug isn't the parameter I'm looking for, I'm looking for something that can technically do what I want, which out of the devices I've seen so far only the Hantek can.
If I come to the conclusion I can't use the Hantek due to software limitation I'll get the DSlogic Pro, and live with the fact it can only due the more basic things I need. But so far it seems the Hantek isn't "dead" yet. Especially considering the SW will keep improving.

I'm still on the fence here though, the two users who have experience with this combo (abraxa and maginnovision) agreeing that it can do what I want, but if I understand correctly there are bugs at the moment that might make it a not so pleasant experience

The reason why I brought up the DSLogic pro is that I'm not convinced that it's limited to 50MHz. It has a Spartan 6 in it, and I don't see a reason why the comparator in the would be limited to the input Crystal frequency. These things are rated to much higher frequencies, and in order to generate a sampling clock of 400MS/s they must be capable of at least that frequency.  My bet is that the actual input bandwidth is higher than 50MHz, as the Nyquist frequency for a 400MHz sample clock is around 160MHz

[toli]

Looks like you are right and it really does support higher BW. I've been watching videos from the OpenTechLab channel on youtube over the last few weeks, so today I've finally watched his review of the DSlogic Plus:
https://www.youtube.com/watch?time_continue=3&v=xZ5wKYnCNcs
Seems like the use of the coaxial leads and the way they implement the input stage really does give a significant advantage when it comes to high speed sampling.it really is very impressive that this small device can get to 200MHz input clock.

So this does make the option of getting the DSlogic plus (with the coaxial leads, no reason for me to keep twisting wires together if I don't have to, for 30$ its worth it ) significantly more appealing than it was until this point. The number of boxes it doesn't tick in my desired spec just got smaller.

I'll try sending DreamSourceLab an email and ask them about the external clock mode. I'd like to understand if there are any other limitation to it and if the threshold voltage is indeed constant for 3.3V CMOS levels. If the threshold level is fixed this will be somewhat of a PITA for me to do this myself every time.
SMB784, do you have any way of feeding a clock into this pin and testing one (or both) of these parameters (maximum frequency it can run at, and threshold level adjustment support)?

[SMB784]

I'll try sending DreamSourceLab an email and ask them about the external clock mode. I'd like to understand if there are any other limitation to it and if the threshold voltage is indeed constant for 3.3V CMOS levels. If the threshold level is fixed this will be somewhat of a PITA for me to do this myself every time.

Judging by their spec sheet on their website tells me that the threshold is continuously variable between 0 and 5V, though I don't know how to do that yet.

SMB784, do you have any way of feeding a clock into this pin and testing one (or both) of these parameters (maximum frequency it can run at, and threshold level adjustment support)?

I will see if I can get my hands on a >100 MHz square wave generator.  If not, then I dont think I can find something that I could use to test this :-/

[toli]

Question is if this 0-5V range also holds for the CLK input vs just the 16 data channels. I think I've seen somewhere a mention that the CLK input is at 3.3V constant, but I can't seem to recall where it was.

BTW, you don't actually need >100MHz square wave to test these parameters. The threshold can be checked at low speed quite easily (and if I'm honest that's the more interesting parameter for me at the moment). For the maximum frequency test a sin wave will suffice. At these frequencies the rise time will limit square waves and they will look more like a sine anyway unless you take extra good care of the test setup. I've actually used sin wave input at 100MHz to the Cypress FX3 IC as a sampling clock because of a similar limitation, and its works like a charm with no issues at all (just add VDD/2 DC offset obviously ).

[Andy99]

I will add my 2cents about current status 4032l+sigrok+PV.
- External clock feature is already in mainline. It's available only for newer version of FPGA (>0). (FPGA could be updated without any problems.) One of the problem of external clock is, that upper layer doesn't know, which time based was captured. You can select only nearest frequency from drop-down menu. I have reported this problem in PV, and hope so, that will be fixed.
- 4032l has HW support from different trigger eg. BUS value, time... . These options are not available in PV now. After that, I could take a look on sigrok with implementation.
- USBXI could be implemented on sigrok, but I didn't find someone, who is requesting this feature.

Regarding to DSlogic, they have separated stream from mainline PV, which have better support. https://github.com/DreamSourceLab/DSView

[SMB784]

Question is if this 0-5V range also holds for the CLK input vs just the 16 data channels. I think I've seen somewhere a mention that the CLK input is at 3.3V constant, but I can't seem to recall where it was.

BTW, you don't actually need >100MHz square wave to test these parameters. The threshold can be checked at low speed quite easily (and if I'm honest that's the more interesting parameter for me at the moment). For the maximum frequency test a sin wave will suffice. At these frequencies the rise time will limit square waves and they will look more like a sine anyway unless you take extra good care of the test setup. I've actually used sin wave input at 100MHz to the Cypress FX3 IC as a sampling clock because of a similar limitation, and its works like a charm with no issues at all (just add VDD/2 DC offset obviously ).

I would be very surprised if the clock input is limited at 3.3V.  I will see if I can find out whether or not this is true.

I'll try the sine wave option, the offset will be the hard part though.  I have a 1GHz signal generator, so I'll play around and see what I can come up with.

[Rolo]

It will not fit the $150 budget for 16 channels but as a tip to all, Saleae does offer significant discounts on their products.  I recently bought a Logic8, got the Enthusiast discount after one request trough their "contact us" form.

https://blog.saleae.com/saleae-discounts/

[toli]

Rolo, I have experience with their tools, they are very nice indeed. However, the price for something that will fit my needs is way out of the budget, so I'm not even considering them.

Regarding DSlogic - I have heard back from DSlab support, and they have confirmed the external clock is fixed at 3.3V level unfortunately.
I will say that the fact they have replied within a few hours is definitely a point in their favor. I haven't heard back from Hantek yet, and I've emailed them over 3 days ago.

[maginnovision]

Rolo, I have experience with their tools, they are very nice indeed. However, the price for something that will fit my needs is way out of the budget, so I'm not even considering them.

Regarding DSlogic - I have heard back from DSlab support, and they have confirmed the external clock is fixed at 3.3V level unfortunately.
I will say that the fact they have replied within a few hours is definitely a point in their favor. I haven't heard back from Hantek yet, and I've emailed them over 3 days ago.

I had emailed hantek some time ago and I think it took a week or two. The biggest difference is they seem to shift most of that sort of responsibility to dealers since they don't, as far as I know, sell directly. If you have issues after you buy one, or even now, maybe contact them. Even if they aren't responsive it'll probably be quicker turn around.

[toli]

I'm not sure sellers of this item can answer technical questions though.

BTW, I've also asked DSlab about the maximum frequency at the external clock port, specifically asking if this can be stretched to 100MHz. They have replied with "about 50MHz". No idea if this is a "safe margin" sort of answer, or practical limit.
I can actually live with 50MHz, this is the fastest clock I've ever used for applications that need external clock for sampling. The fact I will need an external level shifter (which will result in different delay between clock and data) isn't great though.

I think I understand the abilities of the DSlogic Plus well now. Be it the software(s) abilities, and the HW limitations. It is actually something I can live with quite comfortably (except for the need for CLK level shifter that is somewhat annoying).

The Hantek which still seems to have better HW is somewhat of an unknown still.
First unknown is the practical limit on input BW of the signals. The 2.54mm header seems like it has GND on only one edge of the connector. This isn't optimal for digital signal with sharp edges. I'm also not sure what the AST0/1 connections are, I'd expect to see GND in this place:
https://sigrok.org/wimg/d/d7/Hantek4032L_BoxPortSide.png
So no idea how it'll handle a 100MHz clock/data despite the claimed 150MHz.
Second question has to do with this post I've seen online:
https://plus.google.com/113862568356151601304/posts/hknHqNw9Pbc
I couldn't find any other note of it, so there is always the possibility I'll run into such problems too.

Perhaps it would be better to "settle" for the DSlogic Plus, as they say "better the devil you know" 

[toli]

There is some update with this topic, so I'd like to share my findings to help other forum members who might be looking for a USB LA in the future. I know I've had some trouble finding practical information to make the decision.

To sum this up, my main concern with the 4032L following all the other info I've received from the helpful member of this forum has been the actual maximum signal frequency it can handle. The claimed 150MHz seemed too optimistic for the way the output connector is arranged (with GND signal on only one edge of the connector). Lucky for me, member maginnovision was very helpful, and went ahead an ordered a few parts to allow him to test with various frequencies (and I would l like to take the opportunity to thank him once more for all the help). My concern was that the highest frequency won't even reach 100MHz (as I've posted in the last post), and that there are significant differences between channels since ch0 is close to the GND return path, while ch16 is very far from it.
maginnovision did quite a few measurements, but I won't detail them all, instead I will jump to the punch line. According to his findings, with the original leads provided with the 4032L, the maximum frequency you can use is ~90MHz on the channels closest to the GND pins, and ~60MHz on these at the other edge of the connector. This is all with only a single channel used at a time, and will obviously get somewhat worse with multiple channels used at the same time.

In comparison, as can be observed in the video I've posted in one of my previous posts, the DSlogic Plus with the shielded leads seems to support up to 200MHz frequency at the input. I don't need to go that high, only 50-100MHz at most, but I'd like to minimize the chance of missed edges, so the DSlogic seemed like the better option in this regard.
The main issue for me with the DSlogic remains the constant threshold on the CLK pin. However, this I can solve using a level shifter IC. The lower channel count is a point against it, but I can live with it for the foreseeable future. Therefore, I've decided in its favor and placed an order for the DSlogic plus from their website. I've contacted them via email and they have confirmed they are sending the Plus model, despite the site not being updated yet.

I would like to thank you all once more for the help, it was crucial in helping me make an educated decision instead of going on a hunch 

[1anX]

Thanks for all the feedback Toli!
I thought the DSLogic Plus along with their software was pretty good bang for the buck.
I think also that you may have helped a number of others wondering what to buy with your discussion and input in this thread.

[abyrvalg]

I have both DSLogic Plus and Hantek 4032L here for comparison. What test method should I use to determine the bandwidth? Feeding a square wave and counting the edges? Or scoping the channels at FPGA inputs? Thinking about fitting a DSLogic’s test lead to 4032L also.

[toli]

Yes, feed the signal and check what frequency you can use without missing edges/getting false edges.

I was also considering of getting the 4032L and printing a small PCB with proper GND flood and headers for shielded/twisted leads. However, after all the info I've received I just felt like the DSlogic is a safer bet for my current needs.

[abyrvalg]

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal. 400MS/s, 1M samples gives a stable 262144 (1MiB/4 exactly) edge count regardless of the channel used (tried A0 and A15 on the opposite sides of the connector). I have no generator to test higher frequencies quickly, but I'll cook some FPGA config for this (among with some pattern generation to test the external clocking).

Edit: 262144 is the number of periods, not edges (I had both measurements turned on).

[maginnovision]

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal. 400MS/s, 1M samples gives a stable 262144 (1MiB/4 exactly) edge count regardless of the channel used (tried A0 and A15 on the opposite sides of the connector). I have no generator to test higher frequencies quickly, but I'll cook some FPGA config for this (among with some pattern generation to test the external clocking).

Try 20MS and attach a screenshot.

[abyrvalg]

Yeah, getting the false edges now, 10485800+-2 instead of 10485760, both A0 or A15.

[abyrvalg]

DSLogic's result: stable 9998362 edges in 20M samples (DSLogic's M is 10^6, not 2^20). Unrelated clocks runaway?

Funny, it took more time to get the edge count from DSLogic's "polished" software. You can't set a measurement cursor to the first/last sample just by dragging it to the edge - on the left side it happily goes to some hidden negative time area and gets lost there, on the right side you need a highest detail zoom to reach the edge and then the measurement refuses to count the edges silently (solution: it doesn't like the right cursor being at the last sample, move it left a bit).

[toli]

The clocks are definitely not matched well enough to get absolute accuracy at such long record length. The only question is at what point you can see missed edges over a limited period of time.
To get "perfect" sync you'll need to sample with the external clock pins.

Edit:
just in case it wasn't clear what I meant to say, I'll add a few more words. If the clocks are even 1ppm out, you will get 1 cycle missed over 1Mcycles of these clocks. So this is absolutely understandable that the number isn't the round number you expect.
However, if you can find the ratio of the two clocks by sampling a signal that is low enough in frequency so that it is always detected properly, you can count on this ratio to remain almost unchanged for a short period of time. You can then use this info to try ramping up the input frequency until the counted number deviates noticeably from the expected number with the actual frequency ratio of the two instruments.

[TK]

If you need state mode sampling (match signal that changes based on a fixed clock) you need to use the external clock input.  The logic analyzer will sample at every clock edge (rise or fall).  If you are sampling in timing mode, you are going to repeat a certain state and miss others.  It is not going to capture perfectly every single clock edge rise or/and fall.

[wpwrak]

Not even a single line of usable code because they not only didn't want to work with us, they actively sabotaged any effort of upstreaming anything.

Hmm, if they made derivative works of code that was distributed to them under the GPL, and refuse to make their changes available, then you may want to have a chat with the FSF/FSFE. Companies that thought they could get away with disregarding the GPL have been taken to court, and lost. See also https://en.wikipedia.org/wiki/Gpl-violations.org

Of course, if you're talking about code that isn't a derivative work, or if the original was licensed under different terms, then the situation would be different.

- Werner

[wpwrak]

A quick and dirty setup touching an FPGA devboard's 100MHz oscillator pad with HT4032L's test lead shows no problems acquiring a 100MHz signal.

A more accurate test would be to gate the signal to have an exactly known number of cycles. Then you can just trigger on the first edge, grab the sequence, check that the recording isn't cut off, have the cycles counted, and see if the numbers match. If you can use a PLL as clock source, you can also vary the frequency to see when exactly things get interesting.

- Werner

[abyrvalg]

Oops, I didn’t posted the really important numbers: the edge count remained stable over ~10 attempts with DSLogic, but with 4032L there were deviations by more than 100 edges sometimes. Anyway, I’m planning to test it with a clock+counter signals in state mode later.

DSLogic code is open and being updated regularly, it’s just refactored in a way hindering automated merging - not a license violation formally, but looks a bit unfair to the original project.

[toli]

Just a small update, the DSlogic Plus has arrived here very quickly. Its much lighter than I've expected, but seems quite well made. The shielded leads are very nice, even if a bit too stiff. The hooks (as always) are of rather low quality, I will have to look for something nicer to get.

One thing I didn't like in v0.99 of DSview is the change from sample length to sample time. While it makes more sense in many cases, for some of my use cases it would have been better to have it as it was in older version. I hope they will allow users to select which they want to see in the next version.
edit:
seems like the second issue was a misunderstanding and not a bug. Post has been revised.

[dpenev]

Please post the issues in there github repository

Sent from my MI NOTE Pro using Tapatalk

[toli]

I've modified my previous post. The issue with the trigger appears to be the way they've meant for it to work, simply not what I'm used to.
The ability to select samples length instead of time is something I've asked them to add via email, but I'm not sure if they'll implement this. In the mean time I'm using v0.98 instead.

[CB]

I understand the sentiment that using an open-sourced and GPL'ed package without giving back might seem "wrong" to some people, but on the other hand, this is the whole point of the public license.  Most of the Internet runs on software of this kind, and does so without paying anything to the original developers (think Linus Torvalds or Richard Stallman amongst so many others).

Where the developers of Dream Source Labs fell down was in making use of Sigrok without including the GPL license.  When called out on this, they subsequently fixed their errors, and made the source code available.

We shouldn't be angry because that's the way it is supposed to work.

[giubin]

Bad things: the GUI (sigrok fork/ or "being inspired by sigrok") DSView v0.9.7.1 (2 or so years old) was the last public release (but I still prefer ti very much to the original sigrok GUI). The support forum is almost dead, I had a difficult time to setup an advanced trigger but found a work around through the usage of external trigger.

I've just ask trough email at DreamSourceLab for the DSLogic Plus and it's support, and this is the reply:

We are active, and will keep improving our project.
DSView software will be updated to be v1.0.0 version in the near feature.

Thanks,
The DreamSourceLab Tema

[lfldp]

hello ive question
i have dslogic pro version (this is 50mhz version i think)
i cant get sniff 50mhz SPI FLASH communication by using it
mostly i getting junk no MOSI data only MISO when i capture on 100mhz bandwitch i getting MISO/MOSI result but is still not correct SPI log
what could be wrong in my setup ?

[TK]

The DSLogic Pro has a 400MHz sample rate, so you should be able a 50MHz SPI signal

[lfldp]

but sample rate is sample rate and maximum input bandwitch is another case
i think this limitation 50mhz in old dslogic version causes this problems

[TK]

Isn't bandwidth measured on each channel?

[thm_w]

but sample rate is sample rate and maximum input bandwitch is another case
i think this limitation 50mhz in old dslogic version causes this problems

There are some other threads and the sigrok wiki where the differences are discussed.

Things which might matter for performance:
- Probes, do they have internal compensation circuitry
- Is probe wire coax or plain wire
- Internal components forming termination on the board, circuitry may have changed on the newer models?

If you have a decent scope it might give you some clues when probing.

The oldest model uses 0.1" headers:
https://sigrok.org/wiki/DreamSourceLab_DSLogic_Plus
https://sigrok.org/wiki/DreamSourceLab_DSLogic_Pro

[lfldp]

thats right thanks
i have a shorts in original cable perhaps sticker makes this shorts
after removed this sticker and cleaned connector i gets correct log

btw. where i can buy good quality dslogic connector without shorts which will fit to older version which i have ?

[thm_w]

I'm not aware of any sources. You could ask the aliexpress sellers or directly.
At some point I was thinking of making the PCB's myself and then running some 1.13mm coax for cabling (https://www.aliexpress.com/item/32973720198.html or similar).