What is the state of the art for a reasonable DIY LA?

[rhb]

The FeelTech thread makes apparent that there is a significant benefit to  designing an LA using a USB 3.0 transceiver and an FPGA.  Long captures at high effective sample rates are  expensive. This does not make sense.

As a start watch this:



There are a number of under  US $100 FPGA eval boards which with an appropriate analog interface card using an ADCMP561 or similar comparator should  provide satisfactory on the fly compression of the logic signas.

This an invitation to participate in a discussion of what can one easily do with current COTS products to implement a high performance DIY LA.

My guesstimate is that 1 nS resolution logging  of bus traffic at  capacity of disk up to16-32 bits is not unreasonable at under US $200 for a DIY.  About 3x that as a commercial product.  If one only records changes, logging time can be very long at low cost. Saeleae offers this, but at US $1000 i can't possibly justify the expenditure .  At $100 plus "education" it seems a pretty reasonable investment.

[rhb]

Does anyone have experience with the Zybo-Z7?

Many cheap scopes are based on a Zynq chipset.  So building an LA on something like the Zybo Z7-20 seems a rather attractive approach.  It provides important skills for hacking a a lot of low end T&M gear.  It's ~$300 and has 40 PPIOs which appear to  sample at 400-800 MS/S.  I've not yet found whether it takes 1 or 2 clock cycles to store a bus state.     In any case, one should be able to buffer  a significant amount of state in the 1 GB DDR3 memory when logging.

https://store.digilentinc.com/zybo-z7-zynq-7000-arm-fpga-soc-development-board/

If you allocate most of the memory to a ring buffer, you can accept rather long bursts of high speed traffic on the bus.  Large data transfers excepted. There are also a multitude of common bus transceivers  implemented in hardware.  In short, with minimal additional analog hardware, it should do everything one needs out of a medium speed LA

A 400-800 MS/S rate should provide good pulse edge resolution.  And by only sending a timestamp and the changed bits, the average data rate should be tolerable. So logging to capacity of disk should be possible in the majority of cases at very fairly high effective sample rates and very long trace times.

There are lower cost boards, however, it seems to me that tor the effort of building a DIY, something like this offers significantly more  performance for the effort. In addition to the 40 GPIOs, there are USB, uSD, HDMI and 10 /100/1000 Ethernet in addition to SPI.  With a smattering of ADC that might be useful for detecting logic levels on unknown devices.

 i suspect most FPGA boards in this price class offer similar features.  It shouldn't be too hard to make something portable  to multiple devices.

[nctnico]

Don't forget about probe design. Getting multiple channels in may be harder than you think. Using existing logic analyser probes from HP/Agilent or Tektronix could be a good option because these have the passive divider networks right at the probe tips. These are basically multi channel passive divider Low-Z probes.

The Tektronix P6417 for example:
https://www.ebay.com/itm/Tektronix-P6417-Logic-Analyzer-Probe-with-extras/273038533793

[rhb]

The goal is something people will copy and sell on eBay.    A good design licensed such that it generates a strong market in clones.

I have been reading the Digilent Discovery LA description.  The obvious issue is the lack of any input buffering.  So a first order task is to design a 4 channel ADCMP651 or similar front end board that can be plugged onto any LA input to provide buffering.  Using a generic FPGA board one immediately hits the same issue..  I'm hoping that someone with the needed analog design tools and experience will be willing to contribute a set of Gerbers on github.

By making an output adaptor connectable to existing hardware like the Discovery available, a single board should be able to meet multiple market needs. So it's a  product in its own right. Many  FPGA dev boards don't have a good real world interface.  Some glue required.

The Digilent Discovery does most of what the ARTIX Z7-20 does except lacking the ability to sample and process ethernet, HDMI and USB. But neither has the input buffering needed for a proper LA.

[accelc2018]

Yeah, going with Zynq will be a much better solution, since it already has 2x Gigabit Ethernet Cores, and if USB 3.0 is absolutely needed, people can use transceivers like USB3.0 PHY such as TUSB1310A. It should be able to manage 100-150MHz sampling rates easily.

[HalFET]

The probes are the hard part, and often the most expensive part to source. Base units don't cost that much on fleaBay.

But the basic premise of the comparator input is easy enough, though you'll want more than one per channel to detect in between states. It is a flawed assumption that one voltage comparator suffices, having two allows you to implement correct receiver behaviour. It also makes a rising/falling edge trigger less sensitive to noise and glitches.

Another feature frequently missing from cheap hobbyist LAs is the ability to probe a differential bus directly, which is a bit of a shame given an FPGAs abilities in this respect.

[rhb]

The ADCMP562 provides hysteresis, however, the Instek probes use 4x ADCMP561s for each 8 bit probe.  I haven't found a source for a spare Instek probe yet, but that's clearly the easy way to get a probe.

My Zybo Z7-20 came Monday.  This is clearly going to be an adventure as the Xilinx software takes ~50 GB of disk space on Windows 7.  Rather painful download on a 3 Mb/S connection.

It's rather disappointing that Digilent do not sell a comparator Pmod or a fast ADC Pmod.  All the Pmods seem to be Arduino class devices.