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Where is the Keysight Megazoom V ASIC?

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Fungus:
Protocol decoding aside: How much of a limitation is 4Mb of memory if there's good segmentation and good ability to trigger on glitches?

For large amounts of protocol decoding there's probably better devices anyway. The main advantage of protocol decoding in a 'scope is to match analog events to data transmissions. I'm sure Keysight would prefer to sell you a logic analyzer rather than complicate their oscilloscopes.

nctnico:

--- Quote from: mawyatt on February 12, 2022, 02:30:57 pm ---
--- Quote from: nctnico on February 12, 2022, 12:53:37 pm ---Risk in an ASIC can be mitigated by creating programmable (statemachine) blocks. I think this is already the case for the existing Megazoom ASICs.

In the end the choice for an ASIC depends on cost reduction per product, engineering costs and the ability to add extra features. AFAIK the ADC is also included in the Megazoom ASICs so there is a significant cost saving for having 1 chip where the competition needs to buy 3 seperate chips (ADC, FPGA and memory) and 'glue' these together.

--- End quote ---

The likelihood of Keysight being able to integrate an FPGA and ADC of calibre for a quality DSO today is questionable. Back in 2000 when we integrated the first RF/MW System on Chip which had an FPGA, Memory, 3 Processors and a full RF/MW Transceiver the FPGA was the most difficult

--- End quote ---
By programmable I don't mean FPGA but having statemachines that can be programmed using microcode. More in terms of having function specific softcores inside the ASIC. It makes more sense to have a programmable statemachine to implement complex triggering for example compared to creating it in logic anyway. The same goes for math and protocol decoding; a programmable statemachine is likely more effective in terms of amount of logic (chip area) and ASIC validation / testing time. Although care must be taken not to postpone the design & implementations of the algorithms that need to run on the statemachines to the software development phase. Validation of the algorithms must be part of the ASIC development process in order to prevent nasty surprises.

mawyatt:
Another thing to consider about integrating an FPGA, memory and advanced ADCs on a single chip is the looming possibility of a new completely different ADC architecture on the near horizon, which would highly devalue the single chip investment in an FPGA, ADC & Memory.

Something along the lines of the Non-Uniform Sampling type where the "waveform information" is captured in both time and amplitude, and no conventional analog anti-aliasing filter required since the anti-aliasing is "performed" post ADC capture.

SOTA Chip Integration values high quantity usage, where test equipment doesn't qualify. In today's SOTA processes, design cost are astronomical and only justifiable in massive $ markets. Back when LeCroy did their $1M scope they utilized IBMs SiGe BiCMOS 7HP and 8HP process which supported only 180 and 130nm CMOS respectively, and the chip design costs were probably in the few 10s of million $ per chip. Since the CMOS is what the Processors, FPGA & Memory are built in, those features sizes in 7HP and 8HP limit what one can do with CMOS on the these BiCMOS processes, and thus prevented any worthwhile digital implementations on these chips (BTW this is the achilles heal of SiGe BiCMOS!!). Todays design costs in SOTA CMOS are probably 10 to 30 times the investment LeCroy made way back with 7 & 8HP.

So smart test equipment $ likely will focus on just the advanced ADC in whatever process makes sense, and use whatever FPGA & memory required, or roll a custom digital only ASIC which is not an FPGA in whatever processes makes sense. Also don't forget that cramming a bunch of stuff on a single chip increases the chip size, and memory takes up a bunch of space, and chip cost grows exponentially with size.

A complex high performing scope architecture, with FPGA, ADCs, and lots of memory will require an advanced small feature CMOS process to cram everything on a producible size chip, and the design cost and process cost will be unjustifiable considered the limited market.

Best,

2N3055:

--- Quote from: Fungus on February 12, 2022, 02:40:39 pm ---Protocol decoding aside: How much of a limitation is 4Mb of memory if there's good segmentation and good ability to trigger on glitches?

For large amounts of protocol decoding there's probably better devices anyway. The main advantage of protocol decoding in a 'scope is to match analog events to data transmissions. I'm sure Keysight would prefer to sell you a logic analyzer rather than complicate their oscilloscopes.

--- End quote ---
Limitation is that there is NO 4 Mpts of memory. It is 4 divided by 2 for ping-pong buffers, then by 2 for shared channels, and then again by 2 if you use MSO digital channels. So it goes from 2Mpts for single channel best case scenario to 512kpt worst  case...
With segments, even worse.

Example:
MSOX3104T: One channel active. CAN bus decoding. 50us/div, to fit one packet across the screen. Segments set for 64 segments (packets in this case). Sample rate : 12,5 MSa/s.

SDS6104H12: One channel active. CAN bus decoding. 50us/div, to fit one packet across the screen. Segments set for 64 segments (packets in this case). Sample rate : 5 GSa/s.

If you're only decoding, it doesn't matter. If you're looking to see high frequency interference in signal, that confuses devices on  a bus, it matters a lot.

It is not even LARGE amounts of decoding or large time bases... 100us per division already makes it sample at 625MSa/s .
At 200us/div you are already at 250MSa/s that puts you in Rigol 1000Z and Micsig territory.  At 1ms/div you are at 50MSa/s. And that is SINGLE channel per ADC. You enable channel pair, and it all halves. And all the time you are having full 1GHz front end bandwidth piped into it.

As for good triggering on the glitches, even SDS2000X+ has full set of triggers and zone triggers equivalent to 3000T. Rigol 5000/7000 and up also have it all.

Siglents have better analog noise performance, Rigols have 4 math channels, and 4 decode channels.

rf-loop:
Afaik, what ever this matters or not but is it so that MZ IV do not have digital trigger engine. Do it have conventional old side pathway analog trigger system.
And I did not say or made guestion is it good or bad. Only what is fact.

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