Hi. I’m an amateur electronics enthusiast with an interest in retro computing. I found a datasheet for a DRAM chip used in the TRS-80 Color Computer.
https://orchidsound.com/mcm4517p12-dram-16-384-bit-16k-x-1-120ns-pdip-16-motorola/
1. It uses 14 mW when in standby. What exactly puts the chip in “standby”?
When a memory cycle is complete and both the RAS and CAS strobes return to their inactive levels.
2. The chip has “Early write common I/O output capability”. What does this mean?
Not particularly clear from the datasheet but the timing diagrams show that input write data is required, and presumably latched, very early in a memory cycle whereas the read output data only appears late on the memory cycle. This would allow the data input D and data output Q to be commoned and connected to a bidirectional data buffer.
3. It has 64K compatible, 128-cycle 2 ms refresh. What does 64K compatible refer to?
Compatible with later generation 64K (65636x1) DRAMs
4. It has “hidden” refresh. Does this mean that the output on Q remains latched/valid even if you modify the address and assert /RAS to do a refresh?
Correct.
You need to obtain the full data sheet and look closely at the timing diagrams included. These show the sequence of each type of memory cycle and when data and addresses to the DRAM have to be applied relative to the RAS and CAS strobes.