A SBus card for SPARCstation designed in 2020...

[dolbeau]

Hello,

Thanks to the help found in these forums, my insane project is now somewhat working. I've made a SBus card featuring an Artix-7 FGPA for my 90's SPARCstations :-)

To be more accurate, it's a SBus adapter board that takes on a commercial board (ZTex USB-FPGA Module 2.13, as designing the whole thing was way too complicated - it's my first hardware design...

Things are still very rough. If the board tries to initialize early (so it can be seen during POST), the SPARCstation 20 I use won't POST reliably. If I delay the start-up by 20s (hot-plugging also work, but it's probably a better idea to just delay the init ;-) ) , enough for the SS20 to POST and reach the OpenBoot prompt, then I can force a discovery of the board. It will then appear in the device tree - OpenBoot can read my minimalist ROM. I can then map my board's internal 'registers' in virtual memory, letting me write to them from OpenBoot to e.g. change how the board LEDs blink. I'm also able to do some GCM computations in the FPGA from OpenBoot. Next step, doing GCM from inside NetBSD to create a crypto accelerator :-)

Extract from the device tree as seen by NetBSD:

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ss20:~> sudo ofctl  -l | egrep 'SPARC|iommu|sbus|FPGA'
ffd4e630: /SUNW,SPARCstation-20
ffd5b700:   /iommu@f,e0000000
ffd5b890:     /sbus@f,e0001000
ffd76fb0:       /RDOL,SBusFPGA@1,200
But no driver yet:

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ss20:~> sudo dmesg | grep -C1 FPGA
[     1.000006] dbri0 at sbus0 slot 14 offset 0x10000 level 9: rev e
[     1.000006] RDOL,SBusFPGA at sbus0 slot 1 offset 0x200 not configured
[     1.000006] cgsix0 at sbus0 slot 2 offset 0x0 level 9: SUNW,501-2325, 1152 x 900, rev 11 (console)
And a couple of picture. The blue part is a 3D-printed extension to meet the physical requirements (smaller PCBs are cheaper!), the small transversal board on top is the Ztex. On the left are the 96 solder point for the SBus connector and the level shifters (SBus is 5V...), on the right a header for a serial port, JTAG (untested) and micro-sd (untested) and some LEDs in the middle (10 in all).

In the 'live' picture, the fuzzy beaglebone white (top left) is connected by jumper cable to the serial header (one-way) to see the trace of the SBus FSM that my design emit for debugging.

[dolbeau]

Everything is now there:

https://github.com/rdolbeau/SBusFPGA

[T3sl4co1l]

Neat, it works!

Tim

[dolbeau]

Neat, it works!

Yes - and probably wouldn't have without the help from this forum ! 

Still a long way from doing something useful with it, but both the PROM and OS see and talk to the FPGA, so the now it's a matter of gateware & driver mostly...