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how to cheaply-LA a 90s 32 bit board?

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DiTBho:
umm, a secondo problem: the software to monitor the bus!

Those HP machines are(1) for 68k, while in my case I have MIPS signals and opcode.
Plus, all the lines used by the DBG-board need a program to be decoded and used.


Ummm, I'm more tempted to use several LA drives in a chain(1), the kind I can write the software myself

4x 32 channels?
8x 16 channels?
16x 8 channels?



(1) they are modular machines, so they probably also had other modules for other architectures.
However, it seems that you can find more easily (or only) modules for 68k.

DiTBho:

--- Quote from: DiTBho on August 08, 2023, 08:25:43 pm ---Maybe the DBG-board can force longer wait-stage cycles!
(I wish I had the manuals!!! damn mice!)

--- End quote ---

Found a paper manual: the DBG-board can force longer wait-state cycles!
Excellent!

alm:

--- Quote from: DiTBho on August 14, 2023, 09:33:41 am ---umm, a secondo problem: the software to monitor the bus!

Those HP machines are(1) for 68k, while in my case I have MIPS signals and opcode.
Plus, all the lines used by the DBG-board need a program to be decoded and used.

--- End quote ---
No, HP machines have software support for a wide variety of CPUs, but support for some was shipped by HP, while others were sold by third parties and are probably unobtanium by now. Now in addition to the software you often need a hardware interface between the processor / bus and the logic analyzer blade that translates signals from the CPU to something easily usable by the logic analyzer. For example extracting address information even when the address bus is internal to the processor.

Finding the dedicated pre-processors that might only fit a single model from a CPU family is going to be a pain for any logic analyzer. It might be worth looking if someone reverse-engineered them, or if you can live without inverse-assembly. I don't think any of the affordable options that are currently for sale offer inverse assembly at all, so you'd be no worse off. In both cases you'd just get the raw bits/words.

DiTBho:
so, let's assume you'd better use several LA units with Open Source support and write the software by yourself.

I wonder how expensive and feasible it goes this way  :-//

alm:

--- Quote from: DiTBho on August 16, 2023, 11:41:44 am ---so, let's assume you'd better use several LA units with Open Source support and write the software by yourself.

--- End quote ---
Try to find analyzers that have a good input circuit that doesn't load the bus too much at these speeds and that have a state mode in hardware that is fast enough (25 MHz?) in addition to a timing mode. Inverse assemblers and decoders are simpler if they have one sample per clock instead of having to solve the additional problem of extracting data on the edges of the clock yourself, and the requirements on the sample rate and memory depth will be lower. Unfortunately not many of the cheap logic analyzers offer state mode.

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