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how to cheaply-LA a 90s 32 bit board?

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artag:

--- Quote from: DiTBho on August 16, 2023, 11:41:44 am ---so, let's assume you'd better use several LA units with Open Source support and write the software by yourself.

I wonder how expensive and feasible it goes this way  :-//

--- End quote ---

The problem with using multiple analyzers is that they all need to sample at the same instance. The cheap ones don't have an external clock so you have to use a channel (one from every analyser) to oversample an external one and then put the recordings back together in software.
The only software I know of that does this is ngscopeclient, and that currently has very limited support for capture devices.

DiTBho:

--- Quote from: alm on August 16, 2023, 07:33:09 pm ---25 MHz?

--- End quote ---

yes, 25Mhz is the max freq.

DiTBho:
Just found that activating the debug-mode on the DBG-board forces the CPU-module to display the instruction stream addresses on its bus during idle bus cycles!

Great! You can extract them!

Doctorandus_P:
You only need so many channels if you want to do complete state analysis.

If you are just interested in getting the timing right (or verifying it), then a bunch of control signals is most of what you need, and you can use "extra" channels for capturing a few of the data and address bits, but you don't need all address and data bits for this.

DiTBho:

--- Quote from: Doctorandus_P on September 18, 2023, 05:28:00 pm ---You only need so many channels if you want to do complete state analysis.

If you are just interested in getting the timing right (or verifying it), then a bunch of control signals is most of what you need, and you can use "extra" channels for capturing a few of the data and address bits, but you don't need all address and data bits for this.

--- End quote ---

There are several things I need to worry about.

Timing is one of them, but I also have to reverse engineer some ASIC chips that I can't find any documentation for, so I have to sniff their reaction in terms of signals they move(2), plus both the address and the data going in and out of them, and even at the CPU-side that's something I can't do via an EJTAG because the CPU doesn't support it.

I don't have the manual of the main ASIC chip and certain things are not documented in the board manual, so I go ahead blindly; after several attempts, I recently figured out how to force the main ASIC to map "ROM0" to its maximum mappable address space (512Kbyte, not cached), and thanks to that I'm slowly making progress thanks to an EPROM Emulator that speeds up the uploading my replacing firmware, as the network part still doesn't work properly(1) and I need more than 128 Kbytes for a decent gdb stub, a monitor and a udp/ip stack + ethernet driver for the tftpboot client.


edit:
(1) you need to configure the PHY, which again is not documented.
It's memory mapped, here I can try to deassembly the original ROM, but it's a full mess up.
If course I'm studying it, I can load whatever I need via the EPROM emulator and with the original ROM I can also try to sniff what the CPU puts into the PHY registers when it configures the lan. Sniffing with GDB is not possible on the original ROM, because it's neither relocable nor not copied in RAM.
Here, an EJTAG would be more helpful, if only the CPU supported it ...
(2) hw-side, I'm afraid I'll have to replace some components with a CPLD. Also, if I want to expand the bus, there is a bus protocol, again, undocumented: you have to smiff the signals, understand them, and replicate them in your CPLD device.

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