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how to cheaply-LA a 90s 32 bit board?

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DiTBho:
So, my professional customer's boards at work (Windriver) provide convenient headers for attaching logic probes, and they connect directly to HP-logic analyser pod adaptors.

Execellent but
- being Windriver, it needs a very expensive license
- being HP provessional equipment, it's very expensive (and cannot find one on eBay)

At home I am trying to resurrect and repair a damaged IDT MIPS board (1992) saved from the hydraulic press.
One of the peripherical chip is dead and I am trying to replicate with an FPGA (thanks god it's 3.3V), but timing is not documented, and I need to monitor the bus.

Furthermore, the original firmware is also gone as the UV-EPROM was exposed to sunlight without any protective label, resulting in the complete deletion of the contents (I only read 512Kbyte of "0xFF").

At the moment, I am using a ROM-emulator to test the minimal functions
- RAM
- ROM
- CPU
- Uart

This stuff all work, but I can't use the timer0, the PIC and other devices, including the 4 char alphanumeric LCD, because either they through the multifunction chip that is dead, or they passes through a chip whose register mapping and response I don't know.

That's where a LA is *very* usefull, and, good news, the board is already equipped with a connector and an optional additional DBG-board which allows you to hook up a logic analyser to the main address and data bus with minimal interference with normal function of the logic. The clock is 25MHz clock rate, a modern LA shouldn't have difficulties to capture signals with very short setup and hold times, and on my DSO I see there is a little circuit on the DBG-board that generates "strobes" to capture address and data, and to trigger the test equipment.


--- Code: ---d00
..
d31

a00
..
a23

rd/wr
/slot

fc0
..
fc3

clock@25Mhz

--- End code ---
signals on the asynchronous bus

However, we are talking about a 6 layers PCB and 64 channels at least, so ... what to use?  :o :o :o

alm:
Parallel buses with this high channel count is what the HP/Tek/Biomation/Philips/etc  boatanchors were made for until they were killed by buses becoming internal to the processor and going serial, so that'd be my choice.

Your speed and channel requirements aren't crazy, so if you have the space I'd think you could find something in the HP 1650/16500/1670/16700/1680/1690 (Firewire) series with decent memory depth or equivalents from other manufacturers for cheap. Before 1680/1690 HP used m68k and PA-RISC (16700), so you might like the architecture ;). Inverse assemblers are available but usually only for contemporary processors, and sometimes need rare adapters that massage the bus into something easily translatable (e. g. bring out certain flags).

Get something with cables and pods with fly leads. The HP 40 pin pods are available but add up if you need many. Other brands tend to be less available. Adapters to Mictor or 0.1" square pin headers are usually not too expensive in my experience. Shipping might be the highest cost.

If you're looking for a project, you could design your own with an FPGA and external memory. The logic Sump or Openbench Logic Sniffer might serve as inspiration. Buying a 64+ channel solution new will probably be expensive given how much new equipment needs that many channels.

iMo:
Or take an existing fpga you have handy, and simply connect its pins with the internal LA - ie the ChipScope in Xilinx (it will be generated for you automatically, you need to assign the signals to the internal LA, at least 4x256 signals available, afaik) while you will see the signals on the pins directly in your IDE (like ISE14 or Vivado, or Lattice has an internal LA as well).

You wire the fpga's pins to your DUT board and you will get an LA.

Just a crazy idea..

alm:

--- Quote from: iMo on August 08, 2023, 02:43:14 pm ---Or take an existing fpga, and simply connect its pins with the internal LA - ie the LogicScope in Xilinx

--- End quote ---
Interesting. What kind of memory depth can you expect at sample rates like 100 MS/s and up?

iMo:

--- Quote from: alm on August 08, 2023, 02:52:24 pm ---
--- Quote from: iMo on August 08, 2023, 02:43:14 pm ---Or take an existing fpga, and simply connect its pins with the internal LA - ie the LogicScope in Xilinx

--- End quote ---
Interesting. What kind of memory depth can you expect at sample rates like 100 MS/s and up?

--- End quote ---

Would your old HP LA capture 65 signals at 100MSamples/sec and up?

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