For the address buffers, could it be the AEN signal (page 55)?
It seems the chipset includes a DMA controller, and the AEN signal goes high when the DMA controller is the master and low otherwise (if I am interpreting the datasheet correctly). If that is the case, the AEN signal could be connected to the OE/ pin of the address buffers to put them into high impedance mode when the DMA controller will be driving the address bus.
It could be worth getting a motherboard with the same chipset on it, then you can buzz out the signals and see what a manufacturer has done. Theyve likely had a lot of behind the scenes support directly from the chipset manufacturer for queries just like this one, so it would be a good reference platform.
For the SD and XD busses, my interpretation of the BDIR and SDIR signals also mentioned on page 55 is as follows:
BDIR when high connects D15..8 on pins 2-9 to SD on pins 11-18 and D7..0 on pins 2-9 to XD on pins 11-18
BDIR when low connects SD on pins 11-18 to D15..8 on pins 2-9 and XD on pins 11-18 to D7..0 on pins 2-9
SDIR when high connects XD on pins 2-9 to SD on pins 11-18
SDIR when low connects SD on pins 11-18 to XD on pins 2-9
The way I remember how 74x245's work is that when the DIR signal is low, the signals travel from the higher pins to the lower pins, and vice versa.
The datasheet is a bit terse, so it is leaving a lot of room for interpretation and guesstimating what exactly to do.