This question is a continuation of my
earlier question.
In an attempt to learn more about designing a digital input for both AC and DC, I've come up with the attached schematic. My intention is to make the input
active high and have
shorter rise and fall times compared to those seen in the
schematic in the linked question. The input in questions will be connected to an
ESP32.
As per the previous question, the purpose of the polarized capacitor is to even out the on/off switching of U1 when AC is applied.
I'm wondering if this is a viable way to design an input? The rise and fall times becomes rather long (11ms rise/47ms fall to reach required voltage levels) when I try to limit the current draw while the input is active. I'm concerned that during the time the voltage level is between what is considered low and high might cause erroneous reading on the uC. Of course, the fall time mustn't become shorter than the fall/rise of the applied AC for it to have any actual effect so it all must be balanced out.
Would it be possible to reduce the rise/fall times to the uC by the use of an opamp? I know very little of them, but I seem to remember that they can be used to create a nice looking square wave from an analog signal?
Any insights are welcome, but may I please ask you to be verbose in your comments so that I can understand the reasoning behind your answer?
Thank you!