Why use a Bypass Capacitor for EACH IC in the circuit?

[Falcon69]

I manually route everything.  I tried using Dip Trace's automatic routing, and it really does suck.  So I manually route everything, however, takes me several days :/

[eetech00]

Ive had boards made before with traces down to 0.15mm, The pcb manufacture I have doing them, do a good job, SO not worried about that.  I was more worried about arcing. I read somewhere, though I dont remember where, that if traces are too close together, arcing can occur.  Or even noise and false triggers of components.

I don't think you don't need to worry about arching at the voltage levels you working with.

So, if I keep them at least 0.15mm apart, I should be okay?  Does that even go for a signal trace that is 0.2mm wide, next to a power trace that is 0.95mm wide for example?

That spacing seems a little narrow. I'd use 0.010" or 0.012".

So, If I place the 555 and CD4017 together, I can use cer.cap and res for each, and use one tant.cap for those two IC's.  Then for the 7 logic gates, I can put those close together and use a cer.cap and res for each and one tant.cap for them?  Would that be sufficient enough to handle any noise that could occur?

You really should follow best practice and use a cap for each IC supply pin.

eT

[Falcon69]

there will be a 1ohm resistor in series with a 0.1uF ceramic cap on each supply pin of the IC's, I was talking about the added 0.47uF Tantalum Capacitor.  Tim mentioned I don't need to put that on every IC, if they are close together.

And yes, I am placing traces at least 0.25mm apart. I was just saying that the fab house can go down to o.15mm.

Ya, i didn't think I needed to worry about the arcing, seeing how the circuit won't see more then 13.43volts, idea.  Max amps with everything on is just under 6A.

[Falcon69]

Oh, another question.  The 555 Timer has a supply pin 8, and a reset pin 4 that both connect to the supply. So, would I need a cap/res on the pin 4 as well? Or just tie it together with pin 8

[Dago]

Oh, another question.  The 555 Timer has a supply pin 8, and a reset pin 4 that both connect to the supply. So, would I need a cap/res on the pin 4 as well? Or just tie it together with pin 8

8 is the supply pin and 4 (reset) is just a signal pin. You only need a cap for the supply pin. The reset pin draws neglible amount of current so it does not need decoupling.

[Falcon69]

awesome, thank you.

Also, the connection to the bypass caps.

I should not have any vias, or any other connection between the supply pins and the caps, (or resistor, in the case of ground pin) correct?  so It should look like the picture?


FYI, 555 Timer and CD4017 Decade Counter shown.

[eetech00]

I should not have any vias, or any other connection between the supply pins and the caps, (or resistor, in the case of ground pin) correct?  so It should look like the picture?

I don't see any thermals.
All ground connections should have thermal pads connecting each to the ground pour.

eT

[DanielS]

there will be a 1ohm resistor in series with a 0.1uF ceramic cap on each supply pin of the IC's, I was talking about the added 0.47uF Tantalum Capacitor.  Tim mentioned I don't need to put that on every IC, if they are close together.

The resistor is there simply to make the ceramic cap behave like a lossy tantalum so if you put a tantalum in there, there should be no need to make the ceramic lossy anymore.

For high-speed chips with tons of parallel IOs and internal clocked logic (like FPGAs), you would not want to put resistors in the supply decoupling since the edge currents could cause the supply rails and ground to bounce below operating voltage. The lossy decoupling is something you add on top of normal (low-impedance) decoupling if you need to dampen noise, ringing and other junk.

[Bassman59]

Oh, another question.  The 555 Timer has a supply pin 8, and a reset pin 4 that both connect to the supply. So, would I need a cap/res on the pin 4 as well? Or just tie it together with pin 8

The reason the reset pin is tied to the supply is to ensure that the reset isn't asserted (it's not being used).

The only pins that need bypassing are the power supplies.

[Falcon69]

I thought when using vias to connect the grounds of pins to the ground plane (copper Pour) on the bottom, you don;t use thermals.  Only thermals for through hole parts that connect to ground, or for SMD pads that connect to ground for SMD parts that are on the bottom, if any.

Okay, so since I am only using simple 4000 series logic chips, a single 0.1uF capacitor should be good enough?  No need to run a resistor in series and/or a tantalum in parallel with them?  That would save alot of board space.

Oh, the reset pin, it just does not float or tied to ground?

[tautech]

A reset pin is normally high or low only. Datasheet will advise. Sometimes their function is involved in the Truth Table.

IMO and experience only 0.1 uF is needed per IC, although the wealth of experience that has been offered in this thread should not go unheeded. 

One of the most elegant replies IMO was from eetech00:

Without bypass caps, the IC's behavior may not be reliable because the chips are extremely sensitive to voltage fluctuations, either from the power supply or spurious sources, and it can cause input levels or output levels to change unexpectedly, causing erratic circuit behavior. Its best practice to place a 0.1u cap as close as possible to each IC supply pin. This is true for any CMOS IC device, including the 4000 series..

This sums it up well.

[DanielS]

Okay, so since I am only using simple 4000 series logic chips, a single 0.1uF capacitor should be good enough?  No need to run a resistor in series and/or a tantalum in parallel with them?  That would save alot of board space.

Oh, the reset pin, it just does not float or tied to ground?

A single decoupling capacitor close to each chip's power pin(s) should be more than enough for simple logic gates. You can always plan a few extra footprints just in case. If you have long power traces, you will still need a larger decoupling capacitor every now and then to cancel the power trace's inductance and smooth out lower frequency junk.

That reminds me of a 8088 motherboard I had many years ago with tons of 74-series chips arranged in rows and comb-style power distribution. It had large electrolytics on the comb's spine (board/zone-wide decoupling for low frequencies and power supply wiring), smaller electrolytics or tantalum at the end of each tooth (row of 5-10 ICs) and then the local decoupling ceramic cap for each chip.

As for floating pins, you usually do not want to leave inputs hanging since that can cause unpredictable operation. For example, if you do nothing with unused parts of a 74xx04 logic inverter IC and many other discrete logic gates, the unused parts can go into oscillation so you want to tie all unused inputs to either power or ground to force them in a known and stable state.

[Falcon69]

Understand,

So, how long of a trace are we talking here for the power supply and need of a tantalum?  In Diptrace, It tells me the length of EACH trace I click on. Kinda a nice feature.

[T3sl4co1l]

I should not have any vias, or any other connection between the supply pins and the caps, (or resistor, in the case of ground pin) correct?  so It should look like the picture?

I don't see any thermals.
All ground connections should have thermal pads connecting each to the ground pour.

eT

I never use thermals on vias connecting to polys, except when I know they may be used as test points.  'Cuz... thermals are to make soldering easier -- indeed, thermals only make everything else about the via worse

I also usually tent them, which just makes the ground look sexier.  Occasionally it makes nearby soldering easier, but that's not a big deal.

It's always a good idea to leave a few extra-sized, un-tented, thermal'd vias in various nets (such as supply and ground) for those occasions when you do want to tie wires down, though.

Tim

[T3sl4co1l]

So, how long of a trace are we talking here for the power supply and need of a tantalum?  In Diptrace, It tells me the length of EACH trace I click on. Kinda a nice feature.

You only need a few of the damping R+C (or tantalum C with its internal ESR) in the whole circuit, not one per chip.  The 0.1 per chip (ceramic / low ESR) still applies (though you can generally relax that requirement to "0.1 per region", meaning, all chips within a certain trace length from the capacitor, say an inch or two).

[Falcon69]

Okay, so maybe two per board.  My board size is about 2x4 inches.  So maybe I can put one at the beginning of the supply line and at the end of it (the last chip) and call it good?

[tautech]

Okay, so maybe two per board.  My board size is about 2x4 inches.  So maybe I can put one at the beginning of the supply line and at the end of it (the last chip) and call it good?

Alternatively place only the pads for now, populate the PCB, power it up and monitor the PSU rails with a scope and then decide if the extra "targeted" decoupling is necessary.

[Falcon69]

Well, I dont own a scope, or even know how to use one, let alone what too look for if I did own one.  But, for now, I'll place the footprint for the added tantalum capacitors and when the boards come in and I get everything soldered up, I'll test it. If it doesn't work right, I'll add the Tantalum or take them to school and see if I can use their equipment to test.

[DanielS]

So, how long of a trace are we talking here for the power supply and need of a tantalum?

There is no universal answer to that or decoupling in general: the exact amount and type of decoupling that is necessary is application-specific. If you want exact numbers, you need to calculate the spectrum content of your outputs' rising and falling edge, the capacitance of their output traces, the inductance of their power supply, the capacitance of the input buffer at the end of the traces, equivalent lumped capacitance of internal circuits, other trace and via inductances, etc.. Once you know the exact current spectrum of the noise you need to cope with and the levels you need to get it down to, you select your capacitor mix accordingly. This selection may require considering the capacitors' own parasitic inductance on top of everything else.

The 100nF per power pin figure is simply a convenient and relatively inexpensive starting point that works most of the time when you do not wish to do the math for something that should be trivial.

You can always plan for extra footprints to put tantalum caps or MLCCs on just in case, measure supply noise on those pads and then decide what you might need to add there if anything. If supply noise/ripple remains well within the chips' requirements, you do not need to add anything on those extra pads. As someone else said in some other PCB thread: always plan for extra stuff - pads don't cost you anything.

[Falcon69]

okay Daniel.

Sounds like a lot of math to deal with.  I'm learning alot though, and that's what matters most to me.

I appreciate everyone's input and knowledge.  I've added the 1ohm resistor and 0.1uF ceramic (cheaper then adding a single tantalum) to each supply pin of the IC's.  I will add in a footprint for an extra 0.47uF tantalum capacitor at the beginning and end of the Supply line, just in case I need to add those later. The cost of adding the extra footprints is pretty much pennies, if that, in cost of manufacturing boards, but could save the cost of manufacturing NEW boards later to add them.

Thanks Everyone!

Jason

[eetech00]

I thought when using vias to connect the grounds of pins to the ground plane (copper Pour) on the bottom, you don;t use thermals.  Only thermals for through hole parts that connect to ground, or for SMD pads that connect to ground for SMD parts that are on the bottom, if any.

Hi

Yes...that is correct. Thermals, generally, are only for pins (surface mount or thu hole) that must be soldered to a pour. My comment was meant to be a general FYI. I couldn't tell if the board you presented was a finished board, going to be re-worked, or whatever. But your thinking is basically correct.

eT

[Falcon69]

That board was just a mock-up of what I was thinking for the placement of the bypass capacitors for a circuit I am currently trying to draw up.

Having to manually route all the traces takes me a long time.  My current design has something like 150 transistors/mosfets, 200 resistors, and about 15 IC (4000 series logic gates).

I'm sure I'm over thinking my design and that a microcontroller would eliminate ALOT of those components, but I don't have the knowledge level for microprocessors yet.

I'll post up a pick when I get it finished.

[Falcon69]

Well, I think It is done.

The black circles are where the Cap and resistor are for bypass.  One side of a 0.1uF cap is connected to the ground of the copper plane  with two vias and then connected to the ground pin of the IC Chip. The other end of the cap is connected to a resistor (1ohm, or zero ohm if resistor not needed), and the other end of the resistor connected to supply and the +5v input of the IC Chip. The Red circles are the 0.47uF Tantalum Capacitors.  One next to the +5v regulator and near the end of the last IC chip along the +5v supply line.

How's it look?

Sadly, I will need to use two jumper wires on the bottom side. Everything was just WAY to tight. The board is about 49mm x 118mm.  16 outputs to a 2-way LED Assemblies. 4 Inputs for control. Each fused and then a main power/ground input.  The jumper headers are if I want to add an external Buck/Boost to each Left or Right inputs of LED's (8 Left, 8 Right LED outputs).

[eetech00]

hi

Keep in mind the image resolution is not very good, and without a schematic, I make the following comments without knowing much about what the circuit does, or any special signal/power requirements.

but IMO...

1. Seems to be a lot of unnecessary trace bends.
2. Did you experiment using a ground pour on top side as well?
3. Vias look a little large but difficult to tell from the image.
4. Should be a clearance, from any trace or via, to edge of board.

eT

[Falcon69]

trace bends are there to try and maximize the copper pour on the bottom

I haven't poured a top ground, and probably won't, unless you or others advise me to do so. 

Vias are 0.7mm outer 0.35 inner. The manufacture I will use says they can do 0.6mm/0.3mm Should I reduce them to that?  I just though that the bigger I went, the better the copper/tin/whatever will flow and make a good via.

Clearance between traces and everywhere else is no less then 0.2mm. (that's for copper pour to traces, holes, etc. Everywhere else it is no less then 0.28mm)