Ultra Precision Reference LTZ1000

[cellularmitosis]

I've been taking a swing at making my own LTZ board, based on the schematics of Andreas and Dr. Frank:

https://www.eevblog.com/forum/metrology/ultra-precision-reference-ltz1000/msg249123/#msg249123

https://www.eevblog.com/forum/metrology/mx-reference/msg1297126/#msg1297126

I had a few questions:

Question 1: Frank uses very wide traces for +Vz and -Vz coming out of the LTZ1000, to reduce ohmic losses in the traces.  However, my understanding is that once the LTZ1000 is insulated (e.g. in a bit of foam), the majority of the heat egress is through the copper traces.  Here I've tried out a layout which takes the opposite approach: use skinny traces to minimize the heat egress.  My understanding is that the down-side of this approach is that R1 can be considered to have two parts: the 120R resistor, and the trace leading to it, and the trace leading to it has the poor temperature coefficient of copper.  My question is, how can I develop an intuition about which side of this trade-off is better, optimizing the tempco of R1 via fat traces, or minimizing heat egress via skinny traces?

Question 2: I had two ideas for the thermal treatment of R1 through R5.  Either include those resistors inside of the foam which insulates the LTZ1000, effectively creating a tiny oven, or do your best to totally isolate them from the heat of the LTZ1000.  I'm not sure which is the better approach, and I've attached sketches of both approaches.  Keeping them in the oven would raise the temperature of the resistors, which isn't ideal if the the flat spot on their tempco curve is near room temperature (like with Vishay foils), but they would effectively be in a (pseudo) temperature-regulated environment, so maybe that doesn't matter so much?

The thermal isolation idea I have in mind is to laser-cut some rings of EVA foam (marked on the board with silk-screened zones).  The inner ring would be a "hat" with a lid which isolates the LTZ1000.  Then there would be an air gap (with a few ventilation holes in the board), followed by an outer ring of foam, which would be an open-topped column, and the inside face would be lined with a thermal reflector (aluminum or copper foil).  The idea would be to insulate the LTZ1000 (reducing its total heat output via copper trace conduction, convection, and radiation), then have a "chimney" which creates a thermally isolated zone -- thermal radiation is bounced / absorbed by the outer foam ring, and convected away before it can reach R1 - R5.  Thoughts?

Additional notes:

- I've used a 4-layer design, where the outer layers form an EMI shield, joined by via stitching.

- The grey box outline surrounding the board indicates the inner dimensions of a Hammond 1590B diecast case.

I would love to get any feedback on this layout.  I'm reaching into (personally) unexplored territory with this board layout, so if there things which strike you as obviously wrong, I probably don't see them, so please point them out!

edit: "EVA foam", not "EPA foam"

edit2: Hmm, perhaps the convection holes around the foam are hurting more than helping?  They would cool off the LTZ, forcing it to draw more power and just raise the temperature inside of the 1590B enclosure?

edit3: see this thread for the latest boards: https://www.eevblog.com/forum/metrology/px-reference/

[TiN]

I'd get rid of the voodoo holes around the LTZ, and bypassing your question 1 would focus on getting board with uniform temperature gradients around all critical components (resistors/LTZ). If you have small temperature variation over the board, it doesn't really matter, if traces are skinny or fat. Also you don't want to load unbuffered LTZ output to maintain best accuracy, so in typical setup with Gohm DCV impedance or null-meter those resistive losses don't matter.

For Q2, I'd bias toward getting resistors somewhat decoupled, as temperature accelerate aging and drift of the resistor element. Possible benefit may be more for non-hermetic types in epoxy packages, like Edwin's PWW/VPG Z's to smooth humidity impact a bit, but your PCB shows footprints for HZ. Also using HZ for 70K bias resistors is overkill, you can just have 3-5ppm/K in there without measurable difference .

Overall, your board looks cute 

[Andreas]

Hello,

Q1: what you really want is to have uniform temperature at the (critical) pins. And no air flow around the leads.
The KOVAR pins have 39uV/K against copper.
On a heated device you get easily temperature differences of several K between pins.
So I would use equal trace widths for the sense pins.
In this regard your star point (too) near at the ground pin is somewhat counter productive.

Q2: we are all in a learning phase: so why not try out. But be shure to have enough boards to compare the statistics.
It shurely also depends on the resistors (EPOXY) used. Humidity is the main factor.
I have large differences between e.g. vishay S102 / Z201 / 8G16 / UPW50 / UP805 resistors regarding humidity.
And the "sweet spot" of the vishay resistors does only exist in the manufacturers phantasy.
Unfortunately resistors cannot read data sheets.

- I've used a 4-layer design, where the outer layers form an EMI shield, joined by via stitching.

the problem with 4 layer design is that the (critical) components are not between the outer layers.

The cirquit diagram is not drawn correct (ok I am also guilty). C11 C12 belong to the base-emitter junctions of the LTZ1000 and not to protect the resistors. So also the placement of these critical components is wrong.

I have intentionally used SMD X7R for these capacitors to get nearer to the LTZ pins. (you could also use Panasonic ECHU Film capacitors nowadays to reduce microphonic effects).

with best regards

Andreas

[cellularmitosis]

TiN, Andreas, thank you for your feedback!

Andreas, I have updated the schematic to reflect the intent of C11 / C12 -- is this correct?  (attached)

Update: whoops, totally fudged C12.  updating coming momentarily...

Edit: fixed C12.

[MisterDiodes]

Just a few thoughts for Cellular, based on past experience:

1. I would lose the voodoo holes and crop circles.  At least in our tests those are not really helpful in most cases and will actually cause more thermal gradients on the board and make LTZ traces longer than required.  What has really worked much better for us is to let the board heat naturally and evenly in a stable way - any thermal gradients on the board you want to stay steady at equilibrium.  Excess copper around the LTZ tends to make the board react more to changing ambient conditions, which you don't want.

2.  For Vref boards we never use more than one mounting / screw hole.  The moment you add more than exactly one mechanical screw hold-down on a board you've just created a stress riser between the board and it's housing.  If you need more than one screw hold-down, the hold-downs should be compliant (use rubber washers, flex-plastic posts, etc.).  Ideally the Vref board has a minimal mechanical attachment to anything around it, and it should be absolutely free to assume any size it wants to be over time without fighting against the enclosure.

3.  There is a difference between Air Draft protection on the LTZ and Foam "Insulation".  Air Draft protection you need around the leads top and bottom  (and keep those leads short for A version).  You don't necessarily want or need foam thermal insulation around the LTZ because you do need at least some steady thermal flow out of the device for the on-chip heater to stay stable.  If you're using skinny traces and foam insulation you can easily run into a condition where the LTZ is over-insulated - and the end result is a wobbly Vref.  Keep an eye on that.

4. Keep all your current loop areas small. Remember that copper on the board does exactly nothing for low freq mag fields, so the board always goes into a good enclosure shielding system - for wherever this is going to be used.

Again: A very good starting place for LTZ design is to look at the 3458a LTZ Vref board as inspiration, proven over hundreds of thousands of units.  The final result of that board is basically any real drift you'll see is from the LTZ die itself, which is beyond your control - and that's about as good as it gets.

[Andreas]

Andreas, I have updated the schematic to reflect the intent of C11 / C12 -- is this correct?  (attached)

Hello,

it shows the intention.
-> the more essential is the correct placing in layout.

with best regards

Andreas

[kj7e]

Related to MisterDiodes comments above, recently I did some tests with my reference wrapped in open cell foam and unwrapped inside a metal enclosure.  I found less TC drift with the reference board not being wrapped in foam.  So I came up with another low stress mounting idea.  Cut some slots in some felt strips and slid the board into position.  There is a small amount of play to insure there is no stress on the board.

Also like MisterDiodes mentions, my A chip is dropped to the board and I have small closed cell foam caps for the underside of the board and the can itself.  I going to alter this and make a foam ring to shield the pins from the board to the can only with the can exposed above the foam ring.

[Kleinstein]

The traces towards R1 (usually 120 Ohms) is in dead a difficult question. One has to find a kind of compromise between thermal layout and trance resistance.
One thing one can do is to have the traces wider where the temperature gradient is small. So have a relatively thin trace near the reference and a thicker one near the resistor, where thermal properties are less important. Copper resistance near the LTZ is less important than copper resistance away from the chip. Also not every bit of copper resistance is bad - the 400 K compensation resistor suggests that the normal reference circuit will have a certain typical TC and the correct amount of TC added to the resistors could even be an improvement over the 400 K resistor.

The difficult pin on the LTZ1000 is the ground  and to a lesser extend the +7 V pin, as here are several connections going off.  At least the 70 K resistors can share a common trace - likely also with the 13 K/1 K divider. The tricky ones are the 1 K and 120 Ohms resistors to the GND pin.

One does not need super thin traces - the more important thing is a balance in thermal design, so about equal heat flow to all pins. So in areas where several lines run in parallel they should be thinner than the other ones. The idea behind extra copper near the LTZ is to have thermal coupling between the pins and the lines towards the pins - this extra copper only makes sense if used correct. If not well balanced it can do more harm than good.

[cellularmitosis]

Thanks so much for the feedback and discussion, all!

Here's an alternate, simpler, denser idea on a 50x50mm 2-sided board.

edit: a couple of slight routing tweaks

edit2: oshpark ordering link: https://oshpark.com/shared_projects/FH6nJLus

edit3: github link: https://github.com/pepaslabs/px-ref

edit4: see this thread for the latest boards: https://www.eevblog.com/forum/metrology/px-reference/

[TiN]

Such a productivity. I took me 3 years to get from KX to FX, and you cooking them like hot buns non-stop. 
I'd say make all variants, and then try a futile comparison between the different designs. With good amount of luck, we could see the different stability after 3-5 years of measurements. 

[hwj-d]

I'm just watching your very interesting developments right now.
But i can tell, that my constantly with pure 4s 18650 driven kx is very stable, as i can see with my 34461a. 

[Dr. Frank]

I had a few questions:

Question 1: Frank uses very wide traces for +Vz and -Vz coming out of the LTZ1000, to reduce ohmic losses in the traces.  However, my understanding is that once the LTZ1000 is insulated (e.g. in a bit of foam), the majority of the heat egress is through the copper traces.  Here I've tried out a layout which takes the opposite approach: use skinny traces to minimize the heat egress.  My understanding is that the down-side of this approach is that R1 can be considered to have two parts: the 120R resistor, and the trace leading to it, and the trace leading to it has the poor temperature coefficient of copper.  My question is, how can I develop an intuition about which side of this trade-off is better, optimizing the tempco of R1 via fat traces, or minimizing heat egress via skinny traces?

Main idea for these broad traces is having very good thermal conductivity, so that the solder joints of the LTZ1000 pins 3 +4 are approximately on the same temperature as the corresponding solder joints of +Ref and -Ref.
The +Ref PCB track carries the zener current of 4mA, whereas the -Ref track carries about 200µA only, i.e. both collector currents. Evidently, I did not balance both tracks in terms of voltage difference across these paths. So I doubt, that it will make any difference, if you use smaller tracks.

Anyhow, as I have a single sided board, the number of solder joints / thermocouples is reduced to a minimum, and these are pairwise symmetric from the LTZ1000 footpoint to the outer jacks, so cancelling each other.
As all these solder joints are located on one horizontal plane, that should help to equalize the temperature difference between all of them.

2 layers or even 4 layers create much more potential thermocouples (i.e. by the vias), and these are additionally distributed over different planes, like the top side, where you will definitely have a different temperature than on the bottom side.

So I think, that your 4 layer approach is not so good regarding thermal aspects, and also over-engineered, and too costly.
Keep things simple!

Regarding the resistors R1 (120 Ohm) , R4 / R5 (12k / 1k) , and R2 (70k), I arranged them around the LTZ1000, so that the lowest resistor value is closest to the LTZ, providing lowest parasitic track resistance. The influence on the T.C. of the 120 Oh resistor should be quite low.
I think, that's the optimum way, and you should again avoid additional layers.

Question 2: I had two ideas for the thermal treatment of R1 through R5.  Either include those resistors inside of the foam which insulates the LTZ1000, effectively creating a tiny oven, or do your best to totally isolate them from the heat of the LTZ1000.  I'm not sure which is the better approach, and I've attached sketches of both approaches.  Keeping them in the oven would raise the temperature of the resistors, which isn't ideal if the the flat spot on their tempco curve is near room temperature (like with Vishay foils), but they would effectively be in a (pseudo) temperature-regulated environment, so maybe that doesn't matter so much?

The thermal isolation idea I have in mind is to laser-cut some rings of EVA foam (marked on the board with silk-screened zones).  The inner ring would be a "hat" with a lid which isolates the LTZ1000.  Then there would be an air gap (with a few ventilation holes in the board), followed by an outer ring of foam, which would be an open-topped column, and the inside face would be lined with a thermal reflector (aluminum or copper foil).  The idea would be to insulate the LTZ1000 (reducing its total heat output via copper trace conduction, convection, and radiation), then have a "chimney" which creates a thermally isolated zone -- thermal radiation is bounced / absorbed by the outer foam ring, and convected away before it can reach R1 - R5.  Thoughts?

Additional notes:

- I've used a 4-layer design, where the outer layers form an EMI shield, joined by via stitching.

- The grey box outline surrounding the board indicates the inner dimensions of a Hammond 1590B diecast case.

I would love to get any feedback on this layout.  I'm reaching into (personally) unexplored territory with this board layout, so if there things which strike you as obviously wrong, I probably don't see them, so please point them out!

edit: "EVA foam", not "EPA foam"

edit2: Hmm, perhaps the convection holes around the foam are hurting more than helping?  They would cool off the LTZ, forcing it to draw more power and just raise the temperature inside of the 1590B enclosure?

That's all too complicated and over-engineered, again!

I have enclosed the PCB inside a styrofoam box, and omitted the Styrofoam cap on top of the LTZ1000.
This box suppresses any air draught from outside, and lets the whole interior warm up to about 7°C above ambient temperature.
So a certain amount of heat is flowing through this enclosure, to guarantee stability of the oven regulator, but reduces also the oven power for the non-A version.
That's about 16mA @ 12V, 22°C

It was possible to reduce the overall T.C. to near zero by the nominal 400k resistor (R10), so I would not waste any thoughts about an additional oven for the resistors, or a convoluted isolation.

Same goes for the ground plane layer, for EMC suppression, that's also not necessary.
As you have a pure DC application, such a layer makes no sense at all, as the EMC disturbance comes from outside (mains, switch mode PSU, etc.)

Therefore, a simple tuner box all around the PCB is much more effective, as all of my measurements demonstrate. (I.e. not a single glitch anymore, during nearly 100h of measurement)

My approach delivers very good results, like more complicated ones (e.g. from TiN) obviously do also.

You might go ahead with your design, but you'll never get better results, as these existing designs are optimized already.
And I don't see any idea or ansatz in your proposal, why / how this would give any better results.

Frank

[TiN]

Dr. Frank saved us all all that typing,  , cannot agree more. I can only speak for my own designs, the implementation and approach was driven mostly by the end use goal purpose, not the attempt to improve already working solution (reference board that is). In the end we are limited by performance of the zener itself + performance of the measurement equipment + environment isolation (EMI, temperature, humidity) that is.

So "Keithley experimental" design was targeted for compact size, with wide input supply for easy integration within other equipment, providing direct LTZ output voltage. Recent "FX" design was targeted around getting stable output with 10V stange, so LTZ section was even more simplified, using 1013 opamps and using PTF56 70K resistors instead of fancy BMFs. Those are decision I made during the design, rest are just playing around to make PCB look nice.  I'm still waiting for multi-LTZ design from someoone, in attempt to reduce output noise.

[kj7e]

CM, I like your V2 board a lot, if you have some boards made, Ill buy one and build it.

[tszaboo]

So I think, that your 4 layer approach is not so good regarding thermal aspects, and also over-engineered, and too costly.
Keep things simple!

I shall disagree. My design was 4 layer, inner layers were ground. Having these two layers ment that the thermal aspects are much easier to handle. Remember that copper conducts heat 400 times better than FR4. Having a solid ground plane means solving thermal issues and equalizing the thermals for components. You not only need to match the leads of the LTZ1000, but you have a bunch of resistors. Keeping them in pair (and SMD in my case) means that they are much better coupled thermally.

And the cost of the PCB is quite irrelevant when you make more than 1. The LTZ was about 35EUR, last time I've checked, and the PCB is a fraction of this cost.

[cellularmitosis]

CM, I like your V2 board a lot, if you have some boards made, Ill buy one and build it.

Drat, I have already placed my order for the second version, else I would have included a board for you.

Here's the oshpark links if you want to place your own order:

complex version 1: https://oshpark.com/shared_projects/mkNWJ591

simple version 2: https://oshpark.com/shared_projects/FH6nJLus

I'll put it all up on github later today.

Edit: The cap footprints should fit any film cap with 0.2" lead spacing (e.g. WIMA MKS2 (via mouser), or Kemet R82 (digikey)).  The R1-R3 footprints should fit any foil resistor (Vishay with 0.15" or AE with 0.2" lead spacing), and the R4/R5 divider footprint is intended for a Vishay foil divider.  R1-R5 will fit hermetic or not.

edit: see this thread for the latest boards: https://www.eevblog.com/forum/metrology/px-reference/

[Dr. Frank]

So I think, that your 4 layer approach is not so good regarding thermal aspects, and also over-engineered, and too costly.
Keep things simple!

I shall disagree. My design was 4 layer, inner layers were ground. Having these two layers ment that the thermal aspects are much easier to handle. Remember that copper conducts heat 400 times better than FR4. Having a solid ground plane means solving thermal issues and equalizing the thermals for components. You not only need to match the leads of the LTZ1000, but you have a bunch of resistors. Keeping them in pair (and SMD in my case) means that they are much better coupled thermally.

And the cost of the PCB is quite irrelevant when you make more than 1. The LTZ was about 35EUR, last time I've checked, and the PCB is a fraction of this cost.

You're right, that one GND layer might help equalizing temperature differences.

But that's not the aspect, which I highlighted, I clearly focused on the increased number of  thermocouples.. and your description of your 'mysterious' (not published) design does not explain, why this should have less number of thermocouples. Also, it's not convincing, that these SMD components are well coupled to this thermal plane, as there's PCB material in between..

From you and other contributors in this thread, I'm simply missing any proof for the relevance of such proposed "improvements", let it be practical measurements, or profound theoretical calculations.

As long as this is not available, I regard these ideas simply as vodoo stuff, or over-engineering.

Frank

[cellularmitosis]

BOOM! Gauntlet thrown! Bring on the designs!

[kj7e]

Regarding thermal insulation around the chip itself, I'm able to see what Andreas and others have been saying first hand.  Too much thermal insulation definitely has a negative impact of the chips ability to self regulate its temp.  Despite being happy with the TC and stability of my reference, out of curiosity (after all, I'm only doing this to learn and for fun) I decided to ditch the closed cell foam hat for the chip and make a skirt to only shield air currents from the pins.  I saw a smoother, more linear TC curve that became positive over 32 deg C and had to adjust my TC resistor to a higher value, from 300K to 330K.

The foam is only slightly smaller in diameter to the can, so the foam will not make contact with the pins, its just thicker than the cans height above the board, the inner edge can be gently tucked just under the can.


Ill collect proper data and post a good TC plot later today, but here is a screen shot of my first 40 to 15 deg C sweep;


The negative spike the the end is from me getting close to take the photo.  So from 40 deg C start, slight voltage increase, about 1uV around 33 deg C, then slight dip about 27 deg C then flat from 25 to 15 Deg C.

[cellularmitosis]

kj7e, I was thinking of trying the exact same thing -- thanks for the field report!

[MK]

that black foam is usually conductive, just hope no fragments break off in a few years and change things under the LTZ can.

[kj7e]

that black foam is usually conductive, just hope no fragments break off in a few years and change things under the LTZ can.

I checked before using this foam, not able to detect any conductivity.

[dr.diesel]

I checked before using this foam, not able to detect any conductivity.

Humidity might also toss a wrench with respect to the foam, especially considering it's slightly compressed under the LTZ.

[floobydust]

An Interview with “Analog Guru” Carl Nelson, Sept. 13, 2017
http://www.electronicdesign.com/analog/interview-analog-guru-carl-nelson

"...I am now developing a method to do thermal modeling in Spice that takes into account each transistor’s temperature. It’s rudimentary, but it works, and lets you see die temperature unfold in front of you as time proceeds. I plan to include it in a macromodel of the LTZ1000 heated voltage reference, so customers can do thermal modeling as well as electrical. The Spice folks are choking on their lunch when they see this, but I think it’s the wave of the future."

[Kleinstein]

Thermal modeling is nothing new. I remember an old article about thermal modeling OP for low offsets - that was nearly 20 years ago. However the normal spice simulations don't include it. Much of the design of such old chips is using symmetry to get low thermal gradients - so I don't think this will make a big difference for the LTZ chip itself. You can't change the chip anyway.

Humidity should not be a problem so close to the LTZ chip, as the temperature is higher than the normal air temperature. It is more that the high temperature could be a problem for the foam, accelerating aging. Quite a lot of foam foam from the 1960's does not look that good today and at something like 60 C aging could be 10 times faster than normal.