New official Arduno Cinque board uses 320 MHz RISC-V SoC.

[brucehoult]

https://blog.hackster.io/sifive-unveils-the-first-risc-v-based-arduino-a4d07fe7f21f

I've had SiFive's Arduino-compatible "HiFive1" with the same SoC for four months, but this is a whole new level of cred.

The announcement is low on details at the moment, beyond the 320 MHz and that a WIFI/BT chip has been added. If it's the exact same SoC (very likely) then it's got 16 KB of SRAM and 16 KB of instruction cache.

The orginal SiFive board has 16 MB of off-chip SPI flash, but that could obviously be different on this board.

It will be interesting to see if the Arduino version has analogue inputs. That's the main thing the SoC itself (and SiFive's original board) is lacking.

[thm_w]

They are saying it has an ESP32 on board as well.
Just the ESP32 alone would be plenty for most applications. 240MHz and 520kB SRAM, 18 channel 12-bit ADC.

Looks good but don't think it will be cheap when you have two powerful processors on it. Can make programming more difficult as well (at least at the low level).

[ataradov]

FE310 needs a lot more work to be useful for anything. This is another marketing broad.

[brucehoult]

FE310 needs a lot more work to be useful for anything. This is another marketing broad.

While not yet as polished and comprehensive as the competing products made by your employer, I think it's going a bit too far to say there is nothing it is useful for.

[coppice]

FE310 needs a lot more work to be useful for anything. This is another marketing broad.

While not yet as polished and comprehensive as the competing products made by your employer, I think it's going a bit too far to say there is nothing it is useful for.

Its useful for very little. In general, MCUs are about the peripherals, not the core.

[CJay]

Have they fixed the bloody awful IDE and debug yet or do we have to still rely on crappy serial port debugging and no breakpoints etc?

[ataradov]

I think it's going a bit too far to say there is nothing it is useful for.

What are you going to do with all that power if there are no peripherals to get the data in or out of the device?

I wish them luck, and I did support them on the KickStarter, but let's be real, this is a toy at the moment. And peripherals can make or break the MCU regardless of the core.

[ehughes]

Execution from quad SPI essentially makes this a 40MHz part.     I use SPIFI on the LPC series as it is good for boot code, etc but it is very slow. 

I am curious to the amount of SRAM and their target use case.   

[CM800]

So..... what's the point of open source silicon?...


still haven't figured that part out.

[ataradov]

The point is absence of licensing fees an potential lock outs.

40 MHz QSPI is not a huge problem with caches. Embedded flash is better, but in conventional MCU is does not run much faster, there are still a lot of wait states at high frequencies.

[coppice]

The point is absence of licensing fees an potential lock outs.

What is the point of being absent of licencing fees for just one small piece of an MCU? (Yes, try looking at a typical MCU die, and you'll find the CPU is one of the smallest parts of the chip.). Developing a good set of peripherals for yourself is not a cheap activity.

[ataradov]

Developing a working core is not cheap either, it is not a reason to give up.  Over time they will make the peripherals as well. It is not that hard.

[legacy]

It seems pure marketing shit.
As usual 

[brucehoult]

It seems pure marketing shit.
As usual 

"marketing" as in "You'll soon be able to casually wander into your local Arduino/Pi hobby store and pick one up, instead of ordering from a web site in another country and waiting a month"?

That seems like a good thing to me. If it arrives faster than the bloody Due did.

I believe the more correct term is "distribution".

[legacy]

"marketing"

Since all the "arm" products (e.g. Zero, Due, ...) suck, I wonder why don't they stay focused on a replacement for the Teensy platform, which is neither made-by nor affiliated-with them. It's compatible with arduino through external support.

RISC5 is even worse, it's experimental, unsupported, and useless, therefore completely useless for the common Arduino-user.

[ataradov]

They don't have to have all they products to be useful for everyone. Don't like the board - don't buy it.

[legacy]

They don't have to have all they products to be useful for everyone. Don't like the board - don't buy it.

I like none of their products. They are all useless, except those based on AVR8
(e.g. Arduino2009, Mega*, Nano*, etc)

Of course, it's my point.  I won't buy it for sure 

[julian1]

I'm interested. Although I'd like it if they published their implementation and core-ip as well.

[ataradov]

I'm interested. Although I'd like it if they published their implementation and core-ip as well.

Their?  This thing is using FE310, which has everything published. It is not the easiest read though. It is all written in some obscure HDL conceived by Berkley.

[julian1]

I'm interested. Although I'd like it if they published their implementation and core-ip as well.

Their?  This thing is using FE310, which has everything published. It is not the easiest read though. It is all written in some obscure HDL conceived by Berkley.

Risc-v is published as a spec by Berkley no? And SiFive have only published their implementation's synthesized RTL according to Google?

As part of this availability, SiFive also has contributed the register-transfer level (RTL) code for the FE310 core to the OSHW community.

https://blog.hackster.io/hifive1-is-an-open-source-arduino-compatible-risc-v-dev-kit-304c52cfee09

[ataradov]

By RTL they mean synthesizeable. They provide full source code. Link to GitHub above.

But yeah, good luck reading that Chisel. I really wish they went with Verilog.

[julian1]

Thanks for the links. It looks like the Chisel stuff is embedded in Scala.

This respository also contains code that is used to generate RTL. Hardware generation is done using Chisel, a hardware construction language embedded in Scala. The rocket-chip generator is a Scala program that invokes the Chisel compiler in order to emit RTL describing a complete SoC. The following sections describe the components of this repository.

[ataradov]

But implementation of actual interest are the ones that get implemented in the silicon. And I expect that it will be chisel for all of them.

[brucehoult]

(V-scale / Zscale somewhat obsolete but still interesting) https://github.com/ucb-bar/vscale

I don't think that's really correct.

There are three basic free and open microarchitecture designs for RISC-V that have come out of Berkeley:

ZScale is newer than Vscale, and is "current". It's a very small 3-stage pipeline CPU, competitive with Cortex M0-M4. Last I heard, the RocketChip generator was being modified to output ZScale as an option.

The Rocket itself is a deeper pipeline in-order CPU competitive with ARM designs such as A7, A9, A53. By default Rocket is 64 bit, but SiFive modified the generator to produce 32 bit CPUs as well, which is what is in this Arduino and the HiFive1.

BOOM is an out of order design competitive with Cortex A15 or whichever is the equivalent 64 bit. A72? It's the least developed of the cores at the moment.

The first Linux-capable SoCs will be multi-core 1.6 GHz 64 bit Rocket made on TSMC 28 nm and should start to be available around the end of the year. Those will be competitive with the Pi3 or Odroid C2.

[timb]

Execution from quad SPI essentially makes this a 40MHz part.     I use SPIFI on the LPC series as it is good for boot code, etc but it is very slow. 

I am curious to the amount of SRAM and their target use case.

Well, keep in mind that 40MHz QSPI is the equivalent of 160MHz standard SPI, so it's still quite fast!

Most low-end MCUs can't even do regular SPI faster than 20MHz or so; 40-80MHz is common on the mid to high end range of parts.