(V-scale / Zscale somewhat obsolete but still interesting) https://github.com/ucb-bar/vscale
I don't think that's really correct.
There are three basic free and open microarchitecture designs for RISC-V that have come out of Berkeley:
ZScale is newer than Vscale, and is "current". It's a very small 3-stage pipeline CPU, competitive with Cortex M0-M4. Last I heard, the RocketChip generator was being modified to output ZScale as an option.
The Rocket itself is a deeper pipeline in-order CPU competitive with ARM designs such as A7, A9, A53. By default Rocket is 64 bit, but SiFive modified the generator to produce 32 bit CPUs as well, which is what is in this Arduino and the HiFive1.
BOOM is an out of order design competitive with Cortex A15 or whichever is the equivalent 64 bit. A72? It's the least developed of the cores at the moment.
The first Linux-capable SoCs will be multi-core 1.6 GHz 64 bit Rocket made on TSMC 28 nm and should start to be available around the end of the year. Those will be competitive with the Pi3 or Odroid C2.