Well I only have 13 microinstructions rather than ~250. I think writing some test programs to thoroughly test out the operations will be a lot less of a bother than actually designing and building the hardware!
Really? How many instructions then? I thought the PDP-8 had quite a few instructions and if it's a microcoded control unit it would need at least a few microinstructions per instruction and microinstructions for instruction fetch and interrupt polling. How do you get away with so few?
I have the same 8 instructions of the PDP-8 and an only moderately reduced number of its microinstructions. To correct myself though I actually have 19 microinstructions if those of the IOT (input-output transfer) instruction are included.
Just like the PDP-8, only two of the 8 instructions have microinstructions (OPR and IOT).
The 6 memory reference instructions are:
ANDLogical and between operand and current contents of the accumulator (AC) register. Result stored in AC
TADTwo's addition. Same as AND instruction, but performs binary addition (2's complement) rather than ANDing
ISZIncrement and skip if zero. Content of memory location specified transferred into memory buffer (MB) register, then incremented by 1. Result transferred back to specified memory location. If result has become zero, program counter (PC register) incremented to skip next instruction in-line.
DCA Deposit and clear AC. Stores content of AC in memory location specified, then clears AC
JMSJump to subroutine. Contents PC stored in specified memory location. Content of memory location specified then incremented by 1. Result transferred to PC.
JMPJump instruction. Content of memory location specified transferred to PC.
The
OPR instruction, which does not reference memory has the following microinstructions:
IAC Increment AC (self explanatory)
CLAClear AC (self explanatory)
CMAComplement AC (self explanatory)
RALRotate accumulator left. Contents of AC bit-shifted one step left. This operation includes the 1-bit Link (L) register, treating it as combined 17-bit register with the AC
RARAs per RAL but shifts right.
SMASkip on minus AC. Tests bit 16 of AC. If =1 (indicating a negative number in 2's complement) PC incremented to skip next in-line instruction.
SZA Same as SMA but PC incremented only if all bits of AC=0
OSRLogical OR operation between switch register (SR) and contents of AC. Result stored in AC
CLLClear Link (L) bit (self explanatory).
CMLComplement L bit (self explanatory).
SNLSkip on link bit. PC incremented to skip next in-line instruction if L=1
HLTHalt (self explanatory).
That's a "RISC
" instruction set, but sufficient, with a little coding, to perform just about any major computer operation.