Author Topic: Project Yaigol: Fixing Rigol scope design problems.  (Read 60977 times)

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Offline Bud

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Project Yaigol: Fixing Rigol scope design problems.
« on: March 09, 2016, 08:18:34 PM »
Part 1. Preface

This write-up was inspired by an earlier discussion about rigol DS1000Z series oscilloscopes, when a problem was discovered with the master clock oscillator in that line of scopes. The problem was caused by incorrectly selected PLL (phase locked loop) component values and strange programming of the PLL chip that could not be reasonably explained. Details can be found starting from this post by MarkL here:

http://www.eevblog.com/forum/blog/eevblog-683-rigol-ds1000z-ds2000-oscilloscope-jitter-problems/msg552777/#msg552777

Basically, the PLL was wobbly instead of outputting a stable clock signal. Because the clock drove the ADC chip, the jitter was directly affecting the ADC sampling. MarkL took a few screenshots of the PLL spectrum using his spectrum analyzer and the clock looked plain awful. There was no explanation or justification to such poor PLL clock design other than incompetency of the scope manufacturer and lack or absence of quality control on their production line. 

The manufacturer then issued a firmware update that bandaged the problem but did not eliminate it entirely, partially because a proper update required changing the hardware – the PLL loop components on the PCB. The second reason was of the same nature as the one I discovered during this project, and also required replacing the hardware components – more information on this will be provided later in this article.

After that and being still puzzled by the foolishness of this problem in DS1000Z scopes I decided to check  my DS2072A scope. I am sure you’ve already guessed what I found. The answer is yes, same problem with the PLL clock existed in DS2072A. The 1GHz PLL clock was modulated like hell and sometime failed completely, generating plain narrow band noise. I decided to check it a little bit more and see if I can fix the PLL. At the time I did not realize this will become such a sizable investigation which I eventually named the “Project Yaigol”.

During my investigation I observed (and you will see it for yourself as you read) that the manufacturer of these scopes could not make oscillate the circuits that should oscillate, but was very successful in making oscillate circuits that should not oscillate. For that reason I called that company “the masters of reverse oscillation”. To integrate this honorable title into their name, the R letter was flipped. The backwards R is written as “Ya” and pronounced  “ja” as in yacht or yack. Hence the name of the project: “Project Yaigol”.  ;)

In this article I will provide information to DS2000 scope owners how to fix the PLL and how to fix other not less ridiculous problems I found during the investigation. Same as I, you may not at first believe such stupidity can happen. The bad news for you is the problems are caused by fundamental reasons, i.e. not by component tolerances but by bad design decisions as well as by programming that is incoherent with the underlying hardware. The good news is that not much effort is required to perform the fix. Still, it involves SMT work so you have to have appropriate skills and tools to do it. I will be giving instruction in the article as I write and I will summarize it all together in the end, so If you do not want to read the complete article you can jump straight to the last part for a fix guide.

I began looking into it somewhere in April 2015 and it lasted until late June, making notes and taking screenshots. This information has been sitting and waiting since then but I kept postponing writing a post because of other things. I will see if I can do it now and I am going to break it to parts organized by topics. Still may take a couple weeks to complete so please bear with me. Hope this will be to you both entertaining and useful.

Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #1 on: March 09, 2016, 08:20:17 PM »
Part 2. The PLL

Please use the attached PDFs. I had to split to two files because of attachment size restrictions. I may convert to HTML for online read when have time.
« Last Edit: March 14, 2016, 07:02:16 PM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #2 on: March 09, 2016, 08:23:10 PM »
Part 3. The PLL Power Supply

Please use the attached PDF
« Last Edit: March 16, 2016, 05:54:20 PM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #3 on: March 09, 2016, 08:24:31 PM »
Part 4. Other Power Supplies

Please use the attached PDF.

Additional artefacts are here:
http://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg897887/#msg897887
« Last Edit: March 18, 2016, 02:36:50 PM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #4 on: March 09, 2016, 08:26:34 PM »
Part 5. Front End performance

This part deals with the input stage of the scope, i.e. signal path from the BNC jack on the front panel through to the ADC input. Information presented here may be useful for troubleshooting/repair or learning. There is no design errors fixing in this part.

The two scope channels are identical, this is a photo of one channel:

DS2072A_input_stage.jpg


The input BNC jack is at the bottom, together with a relay that connects a 50 Ohm terminating resistor and the resistor itself. The signal travels up through two attenuator stages, passes through a FET transistor buffer, a variable gain amplifier IC with switchable bandwidth in the top part  of the photo and exits on the top left via an ADC differential buffer IC. The signal then is routed straight to the ADC input pins.

Same as with the PLL chip, Yaigol made another foolish attempt to disguise the IC part numbers by lasering them off. But EEVBlog is here to uncovers these secrets for you. The VGA with controllable bandwidth is Texas Instruments LMH6518 900 MHz, Digitally Controlled, Variable Gain Amplifier, and the ADC driver is LMH6552 1.5-GHz Fully Differential Amplifier from the same company.

Gain_stage.jpg


DS2072A can switch input impedance between 50 Ohm and high impedance. However it also has a stupid bug causing the scope forget it was on 50 Ohm between power ups. You work with an RF circuit, you turn 50 Ohm input On, do you stuff, power off the scope for the night, come back couple days later, power it on, measure your circuit again and ...  :wtf:  the ends do not meet. Perhaps need to turn 50 Ohm termination? You go to settings, hmmm....  it shows 50 Ohm is On   :-//  , unless you realize you need to cycle the setting to get 50 Ohm termination back.  :rant:  The stupid thing tells you it is on 50 Ohm whereas in fact it is not. I have not tested if the bug was fixed in the last firmware. It was not obvious in the earlier firmware either, I could not understand a pattern how/when that happened, it did not happen every time.

The following is a VNA screenshot of input impedance on 50 Ohm setting, Yaigol vs Tektronix 2467B 400MHz analog scope. Yaigol traces are red/green, Tek is blue/yellow. Above 100MHz Tek has a better 50 Ohm compliance.

S11 Yaigol vs Tek.jpg


The following is a VNA screenshot of Yaigol on High Impedance setting. Input impedance is capacitive with Cin about 18.5pF.

S11 Yaigol high impedance.jpg


The attenuator has two stages, a reverse engineered schematic is provided below. I cannot guarantee 100% correctness, I did not try very hard, but it gives you an idea about the overall topology.

DS2072A attenuator.gif


Parts annotation in the schematic is arbitrary. I captured the resistor values but did not measure the capacitors. The topology has quite a few frequency dependent correction circuits but if eliminate them, a equivalent schematic at DC can be composed, which was presented in the above picture.
The first stage appears to have 8dB voltage attenuation, the second stage 16dB, which I calculated based on actual in-circuit measurements of a signal passing through the stages - the test conditions are indicated in the above picture at the bottom.

In terms of power the attenuators present 16dB and 32dB attenuation stages, with 48dB of power attenuation when both attenuators are engaged. Interestingly, the overall attenuation of the input stage from input jack to the output of the VGA LMH6518 measured at its output is 32dB. The following VNA screenshot shows attenuation level with both attenuators engaged relative to attenuators turned off. It can be seen that total attenuation of the signal path is about 33dB.

BW limit off with attenuator relative dB.gif


So how come the total loss of the two attenuators is 48dB but we measured only 32dB at VGA output? Apparently the VGA compensates for the missing 16dB loss. This may be kind of stupid, why attenuate and then compensate by amplifying. My guess it is a compromise to have an input stage with wide range of V/Div settings. The VGA chip itself has a variable attenuator and static gain blocks - refer to Fig.57 in the Datasheet. Page 21 of the Datasheet explains how it works together to build a oscilloscope input front-end.

The next stage after the attenuator is DC/AC coupling control circuit (Y214S electronic relay) and the signal splits to AC path via a capacitor and DC path via an IC (that seems to be AD8510) that mixes it with the vertical offset control voltage (bottom part of the following schematic). The composite signal then enters the JFET high impedance buffer. The first stage of the buffer is a JFET N-channel transistor, the second stage is a NPN emitter follower. The buffer topology boils down to two current sink loaded stages shown in the right part of the schematic (you The Art of Electronics aficionados feel free to correct me if I got it wrong).

DS2072A JFET Buffer.gif


The JFET buffer output is wired to the next stage which performs input conditioning magic, i.e. some of amplification/attenuation and the bandwidth control. It is built on TI LMH6518 variable gain amplifier (a link to the datasheet was provided above). This is where your "enhanced" bandwidth lives. It is also the biggest noise generator out of everything else in the analog signal path.

Gain and bandwidth of LMH6518 amplifier is controlled via SPI bus. Gain settings depend on selected V/Div and input attenuator section. The IC provides selectable bandwidth of 20,100,200,350,650,750 and 900 MHz. In Yaigol DS2000 series scopes I guess the first 3 settings are used. So the little beast is capable of some more. I believe this stage also have feeds from the system processor for offset calibration. The amplifier converts single ended input into a differential output and is followed by the ADC buffer amplifier LMH6552 with voltage gain of 2.



Measured bandwidth at the output of bandwidth controlled LMH6518 is shown next, with the 3 bandwidth settings marked. This is a composite image made from 3 separate  measurements with the scope set to 20MHz, 100MHz and Full bandwidth (note we are looking at the hacked scope). The roll-off in the left part of the chart below 3MHz was caused by roll-off of the balun used to take bandwidth measurements and should be ignored.



The 100MHz and Full are not exactly 100MHz and 300MHz, but the ADC driver buffer seems to compensate for it. The following image shows the measured bandwidth of the ADC buffer alone and the combined bandwidth. The overall 3dB bandwidth of the input stage seems to be in the area of 350MHz.



The output of the ADC driver IC goes to the ADC chip via two 47.9 Ohm series resistors.
This completes Part 5 and in Part 6 we will take a look at the ADC.
« Last Edit: March 26, 2016, 10:42:27 AM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #5 on: March 09, 2016, 08:28:06 PM »
Part 6.  ADC performance

Reserved for future updates

For now take look at this post:
http://www.eevblog.com/forum/projects/project-yaigol-fixing-rigol-scope-design-problems/msg907254/#msg907254
« Last Edit: March 30, 2016, 02:39:36 PM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #6 on: March 09, 2016, 08:29:16 PM »
Part 7. Thermal profile

This section has a few thermal pictures taken with my modified FLIR E4 thermal imaging camera.
The hottest area on the board is the ADC and its surroundings, also spreading to the front end under the shielding can as can be seen in the following pictures:





The ADS chip runs hot, as well as its AVDD voltage regulator:




And even the cooling fan itself is kind of warm:



I also made a few panoramic shots. I had no a proper tripod camera holder attachment, so please excise my crude setup:



It was pain in the butt to make panoramic radiometric pictures from a series of 320x240 shots. I recall I had to combine 8 of them to make one panoramic picture. There were posts in Flir E4 teardown thread and others about procedures and tools but in general it was painful and today I even cant remember what I did and how I did it. But once panoramic radiometric pics were complete it was fun to play with them.

I was feeling bad for the poor ADC fellow, so I fitted a lightweight heatsink I got from Digikey on it. The heatsink came with acrylic adhesive, so no mounting hardware was needed. That dropped the ADC temperature by about 20 degrees C. Here is a few shots before and after installing the ADC heatsink.

no_heatsink.jpg


with_heatsink.jpg


Same but  loaded into FLIR Tools software and with measurements over the hottest spots, which were the ADC, its AVDD NCP1117 LDO voltage regulator to the right of it, and the analog front end -5V LDO voltage regulator in the bottom part of the pictures. Wit no heatsink the ADC ran at 84C. With one the ADC temperature dropped to 62C or something, see the cursor measurements on the right side of the screenshots:

flir_no_heatsink.jpg


flir_with_heatsink.jpg


Some of the attached to this post files are the radiometric files (files with "rad" in their filename). If you have radiometric software you can load and play with measurements and palettes.
I will post radiometric version of the above panoramic files separately because of attachment size restrictions.

I think putting a heatsink on the ADC would allow replacing the fan with a quieter model. A quieter fan would almost certainly produce less CFM volume air flow which I think a heatsink could help compensate by more effective dissipation of heat from the ADC. There were complains elsewhere on this forum the DS2000 fan is uncomfortably loud. I did not have a problem with that as I have much more noisy equipment in my Lab, but anyway, just sharing my thoughts.
« Last Edit: March 17, 2016, 06:02:50 PM by Bud »
 
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Offline Bud

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #7 on: March 09, 2016, 08:30:23 PM »
Part 8.  Getting it right.

FLIR radiometric files of DS2072A board are attached.
« Last Edit: March 17, 2016, 05:53:28 PM by Bud »
 
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Online tautech

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #8 on: March 10, 2016, 08:05:28 PM »
Subscribed
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Offline EV

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Offline crispy_tofu

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #10 on: March 10, 2016, 09:06:00 PM »
++1
 

Offline veryevil

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #11 on: March 10, 2016, 11:17:00 PM »
Just bought a ds1054z yesterday!  Subscribed
« Last Edit: March 11, 2016, 12:24:51 AM by veryevil »
 

Offline rigrunner

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #12 on: March 11, 2016, 12:51:04 AM »
Subscribed
 

Offline borjam

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #13 on: March 11, 2016, 12:54:23 AM »
Subscribed, got a 1074Z a couple of weeks ago :)

 :popcorn: :popcorn:
 

Offline Siwastaja

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #14 on: March 11, 2016, 12:55:09 AM »
Ignored thread due to idiots "+1!!!!!11!!1" bumping it one by one so you always get your hopes high that there is some new content here  :palm:  :palm:
 

Offline AlessandroAU

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #15 on: March 11, 2016, 03:20:33 AM »
Can't wait for this. Really hampers using the scope for large ffts with the current pll
 

Offline tino_so

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #16 on: March 11, 2016, 02:56:41 PM »
Looking forward to reading this saga  :popcorn: 

Regards,
Yaigol user.
 

Offline bitseeker

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #17 on: March 12, 2016, 06:33:48 AM »
Thanks for investigating this and collecting all the info. Looking forward to the upcoming posts. :-/O
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Online nctnico

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #18 on: March 12, 2016, 08:47:32 AM »
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Online tautech

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #19 on: March 12, 2016, 11:48:38 AM »
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
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Offline wguibas

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #20 on: March 12, 2016, 12:29:32 PM »
I agree, tell us the fixes, so we can use them.  I think I'll still learn the lesson.  The suspense is killing me :palm: :palm:
« Last Edit: March 12, 2016, 12:35:05 PM by wguibas »
 

Offline bitseeker

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #21 on: March 12, 2016, 02:17:21 PM »
Patience, grasshoppers. Patience. ;D
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Online nctnico

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #22 on: March 14, 2016, 01:42:56 AM »
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
You want to assemble your own car? Build your own oscilloscope? At some point you just have to take things for granted and move on to more interesting challenges. Besides that I'm quite sure the fix in itself will explain what is wrong with the PLL design.
There are small lies, big lies and then there is what is on the screen of your oscilloscope.
 

Offline miguelvp

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #23 on: March 14, 2016, 06:03:47 AM »
I'm looking forward this constructive criticism.
Even for those that won't modify their scope, they will learn the limitations of their test equipment in comparison to the modified one.

win/win  :-+
 

Offline AndyC_772

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Re: Project Yaigol: Fixing Rigol scope design problems.
« Reply #24 on: March 14, 2016, 09:13:07 AM »
Skip the analysis and just post pictures of the fix so people can improve their equipment right away!
And who learns anything from that thinking?  :palm:
You want to assemble your own car? Build your own oscilloscope? At some point you just have to take things for granted and move on to more interesting challenges. Besides that I'm quite sure the fix in itself will explain what is wrong with the PLL design.
Agreed, a scope is a tool for developing other circuits, not necessarily a thing that everyone needs to study in its own right.

Not every dragon slayer also needs to be a blacksmith, even though they might benefit from a sharper sword.
 


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