Altium design rules

[temperance]

I have the following:

A have net's in the schematic with the following net classes PR_GND and PR_425V attached.

I created a query in the design rules:
(InNetClass('PR_425V') AND (OnLayer('Bottom Layer') OR OnLayer('Top Layer'))) where the second object matches Net Class PR_GND.

This design rule seems to work for clearance calculations between:
polygons to polygons
polygon to pad (as shown in the green layer. V_PFC to P_GND clearance)
...

But as shown for the RED layer, it doesn't work between pads and polygons.

Looking deeper into how this works, it seems you can't define copper (Inconsistent naming as well) to pad clearance as can be seen in the highlighted row in the matrix.

It can be solved by adding two rules:
1. PR_425V where the second object matches PR_GND
2. PR_GND where the second object matches PPR_425V.

Of course you can combine that into one query. But why does this order exist and what is the purpose of this order first A then B. It seems Altium doesn't see a PAD with no copper connected as an object. (It works with 1 rule, albeit not correct, if I just add a tiny trace onto the offending pads.)

[free_electron]

First : careful with layer names... the ASCII string needs to be exact... If you change the name of the layer it will not work anymore. Use 'OnOutside' to avoid this. like:  Innetclass('x...') and OnBottomLayer  , OnTopLayer or OnOutside (both in one go)

second : thru-hole pads (and vias) only live on 'MULTILAYER'. Any test against a via or thru pad will fail. These objects do not fall apart into a padstack where each layer has a copy of them. So you explicitly need to include an 'OnMultilayer' .

A pad with no copper connected does not have a netname so it cannot verify the rule. Enable the "allow single pin nets". That will enforce dummy nets. Also beware of pads that do not have a name in footprints. I often see mechanical pads that have no name. Altium warns against that if you try to commit such a footprint. Heed that warning ! Everything must have a name or you will run into weird situations.

[temperance]

Thanks for your reply.

First : careful with layer names... the ASCII string needs to be exact... If you change the name of the layer it will not work anymore. Use 'OnOutside' to avoid this. like:  Innetclass('x...') and OnBottomLayer  , OnTopLayer or OnOutside (both in one go)

second : thru-hole pads (and vias) only live on 'MULTILAYER'. Any test against a via or thru pad will fail. These objects do not fall apart into a padstack where each layer has a copy of them. So you explicitly need to include an 'OnMultilayer' .

I changed all the queries for the internal and external layers and they work fine now.

A pad with no copper connected does not have a netname so it cannot verify the rule. Enable the "allow single pin nets". That will enforce dummy nets. Also beware of pads that do not have a name in footprints. I often see mechanical pads that have no name. Altium warns against that if you try to commit such a footprint. Heed that warning ! Everything must have a name or you will run into weird situations.

Thanks for the tip.