Large copper fills for thermals vs component footprint recommendations

[Psi]

I'm trying to figure out what is and is not acceptable with regard to copper fills under SMD power electronics.
Just in general, less about a specific part.

Parts have their own recommended footprints but you may also want large copper fills to maximize copper for thermals/current flow.
Often parts will have multiple pins that do the same thing. eg, power fets in SOIC-8 package.

Here's an example where it could be routed two ways.
Obviously the 2nd way will be harder to solder by hand due to thermal issues, probably need preheater. But as far as i know they will both solder fine during reflow.
However the copper pad under the part is now defined by Soldermask which is a bit different.
I'm wondering if the thermal/current gains are so marginal that it's better to stick with recommended footprint.

[ajb]

The purpose of the footprint is to ensure a good solder joint, primarily by controlling the exposed copper and the paste volume.  As you note, adding a solid pour underneath of conventional non-Solder Mask Defined pads (where the opening in the solder mask is larger than the copper pad) makes them Solder Mask Defined, and in the process it enlarges the exposed copper by the amount of the solder mask expansion.  That means a larger fillet, so theoretically a slightly larger solder volume is required, but that's probably a non-issue for most larger parts like these powerSO8 transistors, especially if you're adding window panes for the paste anyway.  On smaller pads the change would be more significant, due to the higher perimeter-to-area ratio, but you'd have to calculate the discrepancy to determine where it would require compensating for. 

If you expect the device to be connected to large pours, you can create the footprint with SMD pads to begin with, and then avoid the issue entirely.  In the powerSO8 case, you could just create a rectangular pad for each of the three source, drain, and gate that is at least as large as your current mask openings, void the standard mask expansion (in Altium, set a negative manual expansion value), and then draw the desired exposed copper shapes (roughly the size of your current pads) in the mask layer. 

SMD pads can be challenging on fine pitch devices, since they necessarily reduce the clearance to adjacent pads, so recommended footprints for some devices will show both pad types, like the attached footprint drawing for the TPS25751.  A potential downside to combining pad types is that any registration error between the copper and the mask layer becomes an offset in the exposed copper for the SMD vs non-SMD pads, so you'd have to confirm that the fabrication tolerances are tight enough -- I suspect that's not much of an issue for any reputable fabricator, but YMMV. 

In terms of the benefit of the additional copper, you can calculate that, or just approximate by looking at the number of squares along the path.  Looking at your screenshots, the left option has the equivalent of 1/2 square between the central pad area and the pour above, while the right option has the equivalent 1/6, so has about 1/3 the thermal/electrical resistance in that top layer connection.  The actual difference is probably a bit less, but depends on the part package (exposed bottom pad area, leadframe thickness, die position, etc), plus you have the vias to lower layers to consider, which may matter more or less depending on how the heat and current flow in the surrounding parts of the system. 

[asmi]

The reason many power ICs have multiple pins for the same net has to do with current carrying capacity, and not with thermals (well not directly - obviously thinner trace => higher resistance per unit length => higher power dissipation and voltage drop, but here we're talking about heat transfer from the die to PCB). There are calculators out there which allows you to calculate the resistance of a trace depending on its geometry. So you would pick the second option for higher current, while with lower current you can get away with the first one.

As for thermal flow - most parts with exposed pad(s) are designed to minimize thermal resistance between die and these pads as to allow for the maximum thermal flux, but you also have to remember that thermal flux is proportional to temperature differential - this is why a lot of modern power parts are designed to work up to very high temperatures (105°C is pretty common, but there are plenty of power MOSFETs rated up to 120°C, and yet some more rated even higher than that!) - this way they maximize heat flux allowing it to dissipate more heat from the same physical structure. But - you also have to remember that heat transfer can go both ways, so if your PCB is getting too hot, it will heat other parts which may not be that resilient, or their specs can drift due to elevated temperature. Not to mention that PCB may have reduced reliability due to thermal cycles - since it is made out of materials with different thermal expansion ratios, it can accumulate stress from thermal cycles and eventually fail.

[free_electron]

that's a powerso package ? go find the appnote from NXP where they made a universal footprint that will hold anything from anyone( nxp, infineon , onsemi , IR , and a bunch of others )

Don't enlarge the soldermask more than the width of the actual thermal paddle . The part fill float during reflow and can settle crooked.


Below is what i use

[free_electron]

That design uses constrained paste deposits with venting channels in the mask. The vias are guaranteed to remain open with no mask leaking in the hole. Due to the mask constrain no solderpaste can wick into the vias.
All the misery with floating (part shiftin or rotating) , pooling (solder flowing to one corner of the pad) , voiding (gas bubbles in the solder joint, wicking (solder disappearing in the via hole, starving the thermal pad of solder) are gone with this.

Field proven on hundreds of devices/car in millions of cars , on eVTOL and even been to, and in, space.