5V to 6V

[Tnixsw]

Hi,

I am not sure if this is reasonable, but if I wanted to interface a 5V logic circuit to an old 6V logic circuit could I raise the GND point of the 5V logic by 1V.

cheers

[booscrawl]

Only if you have a device that can maintain that +1V difference without contributing any common mode noise to your circuit, which is likely difficult.

For voltages that close, adaptation seems unnecessary anyway. The V_high and V_low thresholds of either side will likely overlap - no different than running a link between two devices running at 3.0 and 3.6V.

At most you might want to use a resistor on the output of the 6V device so it doesn't burn out the 5V part.

[PCB.Wiz]

... to an old 6V logic circuit ..

What exactly is this old 6V logic circuit ?

[Doctorandus_P]

You have to know the names of the logic levels (TTL, CMOS, and type 4000 series?) before a decent answer can be given. If you have trouble figuring that out, then post the full part number of the IC's you are using.

[Konkedout]

In general this is a solvable problem.  So as other posters said:
1) Be as specific as possible to describe the two circuits you are interfacing.
2) Are the signals going from the 6V logic to the 5V logic, the other way around or both?
3) You probably do not want to be trying to level shift ground....that sounds like a bad idea.....

[kite31]

At most you might need to level-shift the signal. As mentioned more than once above, information is needed on the context and devices.

[amyk]

... to an old 6V logic circuit ..

What exactly is this old 6V logic circuit ?

Old CMOS (4000 series) is the only one I can think of which would be fine with a 6V supply, but we really need more information. All the other logic families I know of are either much higher or lower.

[Tnixsw]

I would like to interface a PIC micro to a PMOS circuit from the 1970's which has 6V logic. I would like to try to replace a failed ROM IC. These are a specialized ROM where the data is 56 bits on a serial interface. The output is to the same serial bus but is opposite to that of an open collector, as it pulls the data line HI for a HI bit and is HiZ for a LO bit.

The PIC can accept input voltages on the IO pins up to 0.3V above Vcc, and can latch up if above this even with a series resistor, and can reliably accept 5.5V Vcc max. Absolute max is 6.5V but I don't know how reliable it will be.

I can drop the 6V with a series diode and resistor divide the input signals, and I thought a single gate running from the 6V supply and control the HiZ output to interface to the bus, so it pulls HI and lets the bus float LO.

I was trying to think of a simple circuit. The PIC has to be a 20 pin SM device, and the space available is the length of an 18 pin DIP IC x 1.5 the width.

[Obin]

Raising ground is generally a bad idea that can lead to silly mistakes later on. A better idea is to keep the ground reference and shift the higher voltages. The good news is that level shifters are not that complex, two FETs and a resistor and you're good to go.

https://www.digikey.com/en/blog/logic-level-shifting-basics

edit: If space is tight, you can find multichannel shifters in a single IC in all packages, like the TXS0108E for example.

[Doctorandus_P]

You should make a diagram to compare all logic input and output voltage thresholds of the logic families you use, such as in:

https://duckduckgo.com/?q=logic+family+threshold+and+voltage+margin+compatibility&iar=images&t=h_

I am surprised about the latchup of your PIC.  Normally "modern" logic is pretty immune to latchup. There is even an application note for pic (16F84) in which mains voltage is directly going to an input pin to use as a zero crossing detection. That AN claims that input current to the ESD clamp diodes can be up to 4mA (from memory, verify this) without damage. But this does imply that those 4mA have somewhere to go. If the complete supply current of your circuit is less than that, then the supply voltage will rise. And of course latchup problems get worse with bad decoupling, lack of a good GND plane etc...

I guess (<- with emphasis) that going from PIC to PMOS works without extra circuitry. From PMOS to PIC, a simple voltage divider may be enough. Something like 2k2 on PMOS output and then 10k go GND. I think those old PMOS / CMOS IC's can output only a very small current, like 1mA or maybe even less. You should really look up those things in the datasheet of your device.

Another option is to connect the output of your PMOS to an N-channel fet, and the drain of the fet to the PIC input, and with internal pullup enabled. This does invert the signal, so you have to adjust the firmware for that.

Using real logic converter IC's is a better option, especially for "high speed" communication.

Yet another option is to simply run your PIC from the 6V supply, but with a silicon diode in series, to drop it's supply voltage to around 5V4.

The good news is that level shifters are not that complex, two FETs and a resistor and you're good to go.

Or turn that around: 1 fet and 2 resistors. The origin of that circuit is an AN from philips and for use with I2C. Because I2C is inherently an open drain bus, it's a near perfect circuit for that. For fast logic, the open drain with passive pullups may be too slow.

[MrAl]

Hi,

I am not sure if this is reasonable, but if I wanted to interface a 5V logic circuit to an old 6V logic circuit could I raise the GND point of the 5V logic by 1V.

cheers

Hi there,

If you raise the ground you have a couple things to think about.  The first is does the 6v logic work with 1v for the logic zero level.  It not only has to work though but it has to work WELL.  If the 6v logic circuit required 1v max for logic zero then it won't work right except maybe sometimes, and even if it is 1.2v it might not work right because the original noise margin would have been 1.2v and now you've reduced it to 0.2v which is a LOT less.

The right way to do it is with a logic level converter.  These have been around for years and they even make a 4 channel board you can get which could work depending on the levels you really need.

It also depends what you need for the signaling.  Does it have to be one way or the other, or bidirectional.
Also, how many channels do you need.

[Tnixsw]

Thanks for the replies.

I probably should have thought about it earlier, but I could try to see if the data bus will work being driven logic Hi at around 5.5V. I don't know how the input circuits will tolerate the slight drop. If it does work, then the PIC can drive the bus HI directly with its 3 state outputs, and a resistive divider on the input should suffice. The bus signals are about 200KHz, 4.5uS Hi, 0.5uS Lo.

I already programmed a separate PIC to generate the required bus signals and the PIC programmed for the ROM responds as expected, but of course at 5V.

[Terry Bites]

A single MOSFET will do it.
I'm old enough to hate pmos and too old to remember it's thresholds.
CD14504 or CD40109?
?MOSFET gate driver for some serious speed.

[langwadt]

Thanks for the replies.

I probably should have thought about it earlier, but I could try to see if the data bus will work being driven logic Hi at around 5.5V. I don't know how the input circuits will tolerate the slight drop. If it does work, then the PIC can drive the bus HI directly with its 3 state outputs, and a resistive divider on the input should suffice. The bus signals are about 200KHz, 4.5uS Hi, 0.5uS Lo.

I already programmed a separate PIC to generate the required bus signals and the PIC programmed for the ROM responds as expected, but of course at 5V.

it would be strange if 5V CMOS logic isn't sufficient Voh to drive 6V logic. for inputs a series resistor of, e.g. 1k would limit injected current to at most 1mA (in the unlikely case that the 6V logic can actually drive full 6V) which is well within limits

[amyk]

Without any schematic it's hard to say, but take a look at how the Intel 8008 was interfaced with TTL; it's a PMOS CPU which actually runs at 14V, but split into +5/-9 to provide TTL-compatible levels.

[Tnixsw]

I am surprised about the latchup of your PIC.  Normally "modern" logic is pretty immune to latchup. There is even an application note for pic (16F84) in which mains voltage is directly going to an input pin to use as a zero crossing detection.

I thought this too when I was trying to make a simple clock using the mains frequency from a transformer secondary for timing.

On looking around, I came across Microchip note TB3013 and it explains how PIC IO circuitry is different now and why inputs must be limited to Vcc + 0.3V. This only affects pins with analog functions, but these can appear on most IO pins now depending on the type.

[Tation]

Sounds similar to the memory ICs of the first hp calculators. If such is the case, they also worked at 5 V.

[Tnixsw]

Sounds similar to the memory ICs of the first hp calculators. If such is the case, they also worked at 5 V.

HP-92 to be exact 

[Doctorandus_P]

With the 4000 series CMOS, the max. operation speed goes down significantly with lower supply voltage. That may be OK for a calculator, but not for a bigger system. I don't know about PMOS, but I assume it behaves similar in this regard.

[Zero999]

Is it possible to power your logic circuit from 5.5V which can also power the PIC?

Failing that, put a diode in series with the PIC's positive power supply rail to power is from about 5.4V and connect all the IO pins via 1k resistors. 600µA flowing through the PIC's ESD protection diodes is not going make it latch up.