Building a pulse generator: puzzled by PCB trace impedance matching

[shapirus]

Every electronics hobbyist sooner or later decides that he must build his own fast edge pulse generator, and I am no exception.

I'm taking one of the easiest to reproduce routes: N fast logic gates (specifically 4 x SN74LVC1G04 SOT-23-5 inverters) having series resistors on their outputs whose values are chosen so as to provide, when connected in parallel, a specific (50 Ohm) source impedance.

High-frequency effects and the respective design considerations is mostly new field to me, so I have read a lot on this topic, but obviously much still remains to be learned.

When it comes to PCB trace impedance matching aimed at minimizing reflections, it seems to be generally accepted that it's not worth bothering with as long as the length of the signal trace (from the driver's output to the output connector's center pin) is short enough for the given operating frequency. Since we're talking about 400-500 ps rise/fall times for the ICs chosen, and the expected trace length will not exceed 1-2 cm, it seems to be the case here, too.

However I want to understand the general principle without taking the "the trace is short enough" shortcut.

Suppose we need to route an output signal trace that's long enough to consider its impedance. Let's also assume that all the resistors, ICs, and their input trace lengths are perfectly matched. We then have several layout possibilities:


A: connect all the resistors in the same spot right at their respective terminals and route a 50 Ohm trace from that spot to the output connector.




B: make individual traces, 200 Ohm impedance each, from each resistor, and join them at the center pin of the connector.




C: same as B, but make each trace's impedance 50 Ohm.




As far as I understand, there are two correct options: it should be A and one of B, C.

What is the correct one between B and C and why?



Now, part 2 of what I don't fully understand, somewhat related.

On one hand, we want to match the signal trace (effectively a transmission line) impedance to avoid discontinuity. With a 2-layer board with the bottom layer used as a solid ground plane reaching the 50 Ohm target requires that the track is made relatively wide: about 100 mils for a 1.5 mm FR4 board.

But on the other hand, increasing trace width also increases parasitic capacitance to ground that the driver will have to work against, potentially increasing the edge transition times.

It looks like we have a trade-off between matched impedance (to maintain signal integrity) and transition speed here.

Initially my idea was to remove copper on the bottom layer beneath the output signal trace and the area under the output connector to reduce the parasitic capacitance seen by the drivers, but now that I have read more on this stuff, in particular, the controlled trace impedance topic, I am no longer sure that it was a good idea.

Would like to hear what would the best approach in this case be, and why.

[tggzzz]

C's impedance at the socket is 50//50//50//50 = 12.5ohms, whereas A and B are correct. I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

The various online calculators will give a hint about the the relevant dimensions.

[shapirus]

C's impedance at the socket is 50//50//50//50 = 12.5ohms, whereas A and B are correct.

That's what I thought, but since transmission lines are special, I wasn't fully convinced about how characteristic impedance works when they are joined like this.

I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV, should be an original part. Conveniently, I have some 187 Ohm 0805 resistors that will suit the 4x topology.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

Yeah, parasitic inductance is what I overlooked. But... Consider a super-wide signal trace, for low inductance, then no copper on the bottom layer for low capacitance... Since Z = sqrt(L/C), we can retain the same Z while decreasing both L and C by the same factor. Apparently this is what effectively takes place as the diameter of coax cables is increased to reduce losses, while maintaining the same characteristic impedance.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

It was after reading (and watching) on this topic that some questions were answered, but even more questions arised .

The various online calculators will give a hint about the the relevant dimensions.

Yeah, and there's actually a nice calculator in Kicad which I'm using. I wonder if it can calculate the trace on the fly as it's laid out in the PCB editor. It probably can't, but I haven't looked into it closely yet.

[newbrain]

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV

If you head to the TI page for the 74LVC1G04, you can find it's IBIS model.
It's a series of tables that give the dependency between output current and voltage under different conditions (e.g. different supply voltages) and the rising and falling waveforms.
The (linear regression) of the V/I slope can be considered a decent approximation of the output impedance.

[shapirus]

If you head to the TI page for the 74LVC1G04, you can find it's IBIS model.
It's a series of tables that give the dependency between output current and voltage under different conditions (e.g. different supply voltages) and the rising and falling waveforms.
The (linear regression) of the V/I slope can be considered a decent approximation of the output impedance.

There's quite a spread between min and max values. It's ok for rough estimation, but I'll better measure the actual parts I have at hand myself -- this will also help to see how closely (or otherwise) matched they are, at least in terms of output resistance.

[tggzzz]

I've used variant A with success, assuming the 74LVG gate output impedance is about 7ohms, and paying very careful attention to decoupling.

I have actually measured output impedance, or, actually DC resistance (HF scenario may be different, and I'll have to test that later as well) at about 12 Ohms, using 150, 200, and 300 Ohm resistor as load at VCC=3.3 V. It's TI's SN74LVC1G04DBV, should be an original part. Conveniently, I have some 187 Ohm 0805 resistors that will suit the 4x topology.

I wouldn't argue with that value, and the IBIS files seem to confirm it is higher than 7ohms. (I hadn't seen the IBIS information when I made my edge generator).

Ultimately you might end up twiddling resistors to see which is best in practice.

Interestingly, if I understand the IBIS file's contents, it looks like the risetime is pretty much what I've crudely measured, i.e 260-300ps.

Where a track is acting as a transmission line, considering its capacitance alone is wrong. You have to consider both capacitance and inductance, and that leads (ho ho) to the characteristic impedance.

Yeah, parasitic inductance is what I overlooked. But... Consider a super-wide signal trace, for low inductance, then no copper on the bottom layer for low capacitance... Since Z = sqrt(L/C), we can retain the same Z while decreasing both L and C by the same factor. Apparently this is what effectively takes place as the diameter of coax cables is increased to reduce losses, while maintaining the same characteristic impedance.

I'm just trying to think if there's any room for improvement, if we talk about the PCB layout, over the classic microstrip with a trace width calculated to have a 50 Ohm impedance. That's of course after the traces are made as short as possible already.

The characteristic impedance of a line depends on the other nearby conductors. Keywords: stripline, microstrip, coplanar waveguide, plus their differential variants.

It was after reading (and watching) on this topic that some questions were answered, but even more questions arised .

The various online calculators will give a hint about the the relevant dimensions.

Yeah, and there's actually a nice calculator in Kicad which I'm using. I wonder if it can calculate the trace on the fly as it's laid out in the PCB editor. It probably can't, but I haven't looked into it closely yet.

The calculators are all approximations, of varying validity.

Have a look at coplanar waveguide and microstrip, and compare the sensitivity to changes in dielectric constant and thickness, and track/gap dimensions. Horizontal spacing is much better controlled than thickness and dielectric constant.

Then have a look at microwave stripline filters

[shapirus]

HF scenario may be different, and I'll have to test that later as well

It is. Not much, in absolute values, but at VCC=3.3V, when sourcing current into a 200-Ohm load, the ...1G04 has (have: they are quite nicely matched indeed, within ~2% at DC, much of which may be caused by the measurement error) frequency-dependent output resistance: from ~12.5 Ohm at DC to 13.6 Ohm at 5 MHz, 16.8 Ohm at 16 MHz and 20 Ohm at 20 MHz.

However, this may very well be the effect of the parasitic inductance of connections, and now that I'm writing this, I really think that it's the major contributor. The chips I tested were installed in a SOT-23 ZIF socket with certainly more than negligible length of contacts, legs and traces of the breakout board. These few added ohms can very well be attributed to them.

But it doesn't really matter too much in any case. Relative to the the ~190 Ohm series resistance on the output of each gate these few extra ohms will mean almost nothing in practice.

[tggzzz]

(Wrong attribution for the HF scenario!)

A secondary effect of lead inductance is that the L^di/_dt can reduce the drive to the output transistors, thus increasing the transition time. That can look like extra increased resistance.

One advantage of paralleling the driver+resistor is that it reduces such effects and allows each output to switch a little faster.

In the end there is some degree of suck-it-and-see.

[shapirus]

A related question (since it's the same pulse generator that I'm talking about). What output voltage do I actually want? Need help choosing.

Input power will be USB 5 V. Thus I can do e.g. 3.3 V or, say, 4.7 V, where the 0.3 V difference will drop on the LDO linear regulator (might go a bit higher, as the LDO still allows that, but I want to have that extra margin for poorer input say 4.9 V etc.).

- 5 V output makes it a bit more tricky to lay out the board well. In any case I will have the 3.3 V rail to power the oscillator part, which starts to consume increasingly (disproportionally) more power at 4+ V, and that includes the crystal drive level, so I want to stick with no more than 3.3 V for that part, whereas the output driver part can be powered by up to 5 V no problem. So with 3.3 V output I will need to route just one power rail, and two with 5 V; and that's on a 2-layer board.

- 3.3 V-powered driver potentially means a shorter output rise time, because it is probably limited by the output stage's slew rate: thinking it may simply take more time to go from zero to 3.3 V than from zero to 5 V.

- on the other hand, the output driver (74LVC) may be faster at 5 V, which is definitely the case for propagation delays, but it's not the propagation time I'm after, but the transition time -- will it be affected by the supply voltage? The datasheets are silent about this.

- any other considerations to prefer one over the other? Right now I'm building this pulser just out of curiosity to explore the behavior of the oscilloscope, to watch reflections in cables, compare different probes against each other and a 50 Ohm cable connection, etc., and these applications don't require any particular signal level: all they care about is the transition times and the pulse length. Maybe there is some specific application for such a pulser that I'm not thinking about at the moment that would warrant going for the (almost) 5 V output?

[tggzzz]

See https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941

If you have a 5V PSU and 50ohm matched impedance, you will only get 2.5V into scope.

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Why are you using a crystal oscillator if you are only interested in the risetime? Just use the standard R+C+schmitt relaxation oscillator.

[jonpaul]

https://www.leobodnar.com/shop/index.php?main_page=product_info&products_id=295

40 pS.

Direct to BNC for scope.

USB power

Jon

[shapirus]

See https://www.eevblog.com/forum/testgear/show-us-your-square-wave/msg1902941/#msg1902941

If you have a 5V PSU and 50ohm matched impedance, you will only get 2.5V into scope.

Yeah I've seen that post. Of course the voltage seen by the scope is divided accordingly.
Quite impressive rise times for an off the shelf dirt cheap logic gate -- that's why I decided to go this way.

BTW, as a side note, speaking of off the shelf parts, here's what I was able to achieve in my previous pulser that was not aimed at particularly fast transition times, but was intended to produce pulses of adjustable length, amplitude, and frequency: 60 ns to (iirc) 15 us, 3 V to 12 V (before the 50 ohm source series resistor), 1 Hz to 110 Hz.

Output is a push-pull BJT complementary pair -- and no fancy transistors here -- as a matter of fact, it's the TO-126 (!) cheap noname "X values 10 pcs each kit" stuff from aliexpress.

Here it is connected to the scope via the shortest path possible, a BNC male to male adapter and a feed-through 50 ohm terminator:

1. Max amplitude




2. Min amplitude




Not bad at all for this kind of output stage, I would say.

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Interesting. Do you remember (or can you check) if the transition times increase linearly as the supply voltage is lowered, or there's any sweet spot in the middle? This may make going for 5 V worthwhile.

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Yeah, decoupling is yet another rabbit hole. I'm now researching this topic to understand what/how is the best I can do with a 2-layer board, hand soldering, and 0805 parts (of course, no doubt, after the board layout is already done -- but redoing the caps is easy enough). Could go with 0603, perhaps, but hey, that's already at the edge of staying within reason for a DIY board. It's not THAT critical, just want to achieve a reasonable maximum with what I have and can do.

Why are you using a crystal oscillator if you are only interested in the risetime? Just use the standard R+C+schmitt relaxation oscillator.

Just for the heck of it, basically. For one thing, this is an opportunity for me to play with a crystal oscillator and see how it behaves. And now that I've built a decent one, why not use it, especially given that I have enough space for it on the board? Never hurts to have a stable (and also I'll make it user adjustable) repetition rate with low(ish) jitter.

[shapirus]

https://www.leobodnar.com/shop/index.php?main_page=product_info&products_id=295

Of course I know about Leo Bodnar's pulser. But I want to build a pulser, not buy one. I could repeat the design, but for a number of reasons I'm going with a different output stage driver for now.

[shabaz]

Just for ideas, the photo below shows my basic fast-edge generator (it generates approx square waves, with a switch to select 0.1/1/10 MHz). It's not brilliant, so you probably won't want to directly copy it, but maybe there are ideas to rule in or rule out.
I just kept the signal traces as short as I could, there's not much length to the transmission lines, and it's not very well designed, I think I've got around 120 ohm characteristic impedance with the trace width. I used 200 ohm resistors, they have not been optimized, although I would have liked to work on it further at some point.

In terms of performance, I see 480 ps rise, and 420 ps fall times. This was with an On Semi MC74AC02DG (bought from a distributor, so I know for sure that's the part and mnfr that was used).

If I was going to do it again, I'd make these changes:
1. Maybe try to guesstimate the lead length differences for the signals inside the SOIC chip to compensate a bit for that (or use a smaller part)
2. Improve the transmission line characteristic impedance
3. Maybe not use the LTC1799 because it's expensive for what it is
4. Maybe add another switch for an additional few frequencies inside each decade
5. Although it works at 3-5V, maybe add a USB connector for power instead of the barrel socket, and have a 3.3V regulator that can be bypassed with a switch, so that both 3.3V and 5V outputs are easy to select
Other than that, I was generally OK with it, obviously, it's nowhere near state-of-the-art rise/fall times, but still handy from time to time (and I really didn't want to spend £100+ on a ready-made pulse generator that I would rarely use).

[metebalci]

On one hand, we want to match the signal trace (effectively a transmission line) impedance to avoid discontinuity. With a 2-layer board with the bottom layer used as a solid ground plane reaching the 50 Ohm target requires that the track is made relatively wide: about 100 mils for a 1.5 mm FR4 board.

Avoiding a 4 layer board on purpose ?

[Mahagam]

Only one 100n capacitor (C2) is not enough. Perhaps this is the reason why falling edge faster than rising.

[David Hess]

In terms of performance, I see 480 ps rise, and 420 ps fall times. This was with an On Semi MC74AC02DG (bought from a distributor, so I know for sure that's the part and mnfr that was used).

Where is the 250 MHz ringing coming from?  My guess is insufficient decoupling of the MC74AC02DG.

Where is the preshoot coming from?  It starts too early for it to be from the inputs of the MC74AC02DG.  This might also be caused by insufficient decoupling of the MC74AC02DG if power is sagging from earlier in the circuit.

When the MC74AC02DG switches, it connects its outputs to either Vcc or Gnd, which extends the transmission line length from its outputs through Vcc or Gnd.  Decoupling of a power stage requires a lot more capacitance and lower impedance.

[shabaz]

That 100nF had been on my mind too. I've added two capacitors to it (100pF alongside it, and then a 10uF 25V X5R on top).
It has improved the risetime very slightly (not much unfortunately).
Maybe it still needs a lot more capacitance I'll dig around for a 22u X7R and add that instead of the 10uF.

I've attached a render of the entire PCB, the derivation of the supply from the C1 instead of directly from C3 was a bit naughty too, but that's easily fixed by cutting the trace and connecting a jumper wire more directly.

Not sure what else to try on the current board layout unfortunately : (

[shapirus]

Avoiding a 4 layer board on purpose ?

Sort of. For a homemade board, 4 layers is just not viable, and if I order at a fab house, then, even though the price increase compared to 2-layer isn't too high, the shipping time of at least three weeks (no direct airmail now, everything goes via transit countries) is going to kill all the fun. So I'm going the homemade route. Besides, I would first want to build a prototype anyway, and once a prototype is ready and working, I would hardly need to have another copy.

Two layers are actually almost fine. Yes I had to make holes in the ground plane here and there, and route a couple of traces, but there are no splits where it would matter, and I did pay attention to how the return currents, per my understanding, will flow, and avoided creating any ground plane discontinuity there.

[shapirus]

Maybe it still needs a lot more capacitance I'll dig around for a 22u X7R and add that instead of the 10uF.

You don't need capacitance, instead you need to minimize inductance. Some good food for thought and visual demonstration of switching effects can be found here:



It doesn't answer all the questions though, but still that's a good one.

Not so long ago someone on this forum suggested a clever trick of using a small (e.g. 0603 or 0402 depending on your PCB) capacitor inside a non-plated hole, one end being right at the VCC pin, another soldered to the ground plane. This makes the inductance loop one via length shorter :).

There are also low-inductance side-terminated capacitors, see https://www.montana.edu/aolson/ee433/caphfmodel_ieee.pdf. Useful when you really need to squeeze out every last bit of the parasitic inductance.

[shabaz]

I think you're right. I had hoped that the multiple via-holes around the capacitors would have helped, but such pulse generators need a lot more consideration.
I took the decoupling a lot more seriously in the photo below, with 100nF+100pF, flanked by two 10uF X7R capacitors. Also changed the far-away capacitor to a 220uF electrolytic, and wired it directly. And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling. I gained a few picosecond improvements here and there, but actually that last capacitor made most difference; the rise-time has improved a reasonable amount.
It's probably diminishing returns at this point, unless a better package was used other than SOIC to help reduce inductance. It might improve the shape too, since there could be interactions due to discrepancies in length of signals due to the SOIC package, which I didn't take into account.

[metebalci]

I took the decoupling a lot more seriously in the photo below, with 100nF+100pF, flanked by two 10uF X7R capacitors.

My understanding is with SMDs using smaller values for decoupling is not important. Because all has similar inductance. If you can go for a smaller package ok but otherwise the best is to use a single large value (or two same values etc.).

Edit: also you can use a wider trace from decoupling cap to IC and gnd vias.

[shapirus]

My understanding is with SMDs using smaller values for decoupling is not important. Because all has similar inductance.

Well, sort of, yes, if we're speaking about the inherent inductance of the package, but then, let's look at the impedance vs frequency graphs, which very clearly indicate the difference in... let's call it, apparent inductance.

For example, for cap values from 100 pF to 10 uF in x10 steps, all in the 0805 package:



(https://ds.murata.co.jp/simsurfing/mlcc.html)

If this characteristic is applicable for determining the bypass capacitor values, then for each given frequency there will be a specific capacitor with the lowest impedance that will work best.

If I understand it correctly, then, say, 500 ps rise time roughly corresponds to ~1 GHz frequency, and so the best decoupling cap to serve the transition edge would be one with the impedance notch at this frequency. It must, at the same time, store enough charge to provide the required current during the transition until the "slower" bulk capacitors catch up and begin providing power at the high level of the pulse.

This is where the idea of parallelling several capacitors of different values comes from. It doesn't however, always work as expected: see Dave's video:



also see https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values (I have yet to read this one -- it's opened but waiting).

[metebalci]

also see https://www.signalintegrityjournal.com/articles/1589-the-myth-of-three-capacitor-values (I have yet to read this one -- it's opened but waiting).

This would also be my source for the info, from Eric Bogatin's book I believe I read the last time

[tggzzz]

That circuit works below 1.5V (use a bench PSU), but with "noticably" increased risetimes

Interesting. Do you remember (or can you check) if the transition times increase linearly as the supply voltage is lowered, or there's any sweet spot in the middle? This may make going for 5 V worthwhile.

Higher voltage => faster. It is because you are driving the (internal) transistors harder with higher currents.

Make sure layout and decoupling is very good; di/dt of 50mA/250ps interacts with L

Yeah, decoupling is yet another rabbit hole. I'm now researching this topic to understand what/how is the best I can do with a 2-layer board, hand soldering, and 0805 parts (of course, no doubt, after the board layout is already done -- but redoing the caps is easy enough). Could go with 0603, perhaps, but hey, that's already at the edge of staying within reason for a DIY board. It's not THAT critical, just want to achieve a reasonable maximum with what I have and can do.

Poor decoupling can lead to a poorer waveshape; that's the principal reason for ensuring it is as good as possible.

Two points: 0306 would be better than 0603, and watch out for the capacitor's value when it has 5V across it. You can "lose" >80% of the capacitance that way, so check the specs

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

There are lots of things I want to do

[shapirus]

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

Ha. I am going to do a VCC copper pour on the upper layer. It will add another 30-40 pF of distributed capacitance (size of the board is only 33 mm x 53 mm, I designed it for a specific housing), so in terms of energy it's not going to help much, but it might help that fast edge a little bit -- who knows what impedance it'll have at the target frequency. It is considered to be useless to design for interplanar capacitance, unless the dielectric between the planes is really thin (say 0.2 mm or less), but I'm gonna try it anyway. It can't hurt, unless... I'll keep an eye on the resonance/ringing that you mentioned, and experimenting with that is another purpose of trying the VCC copper pour. My intuition, however, tells me that the effects, if there will be any at all, will not be measurable/observable with my DHO804 (enhanced to DHO924 sans AWG&LA), and I'd need a much more advanced scope for that.

[shapirus]

and watch out for the capacitor's value when it has 5V across it. You can "lose" >80% of the capacitance that way, so check the specs

Yes lol I haven't yet finished my tester of the MLCC capacitanse loss under DC bias, it still sits almost fully functional on a solderless breadboard. I will, eventually, but now I have more interest in this pulser.

I have a lot of 100 uF 1206 ceramics from aliexpress -- even their working voltage is not specified, let alone capacitance curves lol. I've measured their breakdown voltage at ~70 V, so they'll be fine in this regard for 5 V, but since they are likely rated for 6.3 V (at best), I'll consider their capacity at 5 V to be say 20% of the zero-bias one, whack more of them on the board, and call it a day.

These are only for bulk energy storage / filtering, of course. For IC decoupling, I've got some better 0805 caps, some C0G/NP0, where they were available for given values, otherwise X7R, with known working voltages. I have yet to decide which values to use, though.

[tggzzz]

I'm considering re-spinning the board on 4 layers, just for the hell of it and to learn KiCAD. But first I want to understand how solid Vcc/Gnd planes resonate, and how to damp that.

Ha. I am going to do a VCC copper pour on the upper layer. It will add another 30-40 pF of distributed capacitance (size of the board is only 33 mm x 53 mm, I designed it for a specific housing), so in terms of energy it's not going to help much, but it might help that fast edge a little bit -- who knows what impedance it'll have at the target frequency. It is considered to be useless to design for interplanar capacitance, unless the dielectric between the planes is really thin (say 0.2 mm or less), but I'm gonna try it anyway. It can't hurt, unless... I'll keep an eye on the resonance/ringing that you mentioned, and experimenting with that is another purpose of trying the VCC copper pour. My intuition, however, tells me that the effects, if there will be any at all, will not be measurable/observable with my DHO804 (enhanced to DHO924 sans AWG&LA), and I'd need a much more advanced scope for that.

...0.2mm... How thick is prepreg on a 4-layer board?

[shapirus]

...0.2mm... How thick is prepreg on a 4-layer board?

No idea. I'm staying away from 4-layer for the time being, there's a lot to swallow as it is besides them for me.

But in any case, interplanar capacitance will make more sense on a 4-layer board than on a 2-layer one, that's for sure. Exactly how much more is a different question.

[David Hess]

It's probably diminishing returns at this point, unless a better package was used other than SOIC to help reduce inductance. It might improve the shape too, since there could be interactions due to discrepancies in length of signals due to the SOIC package, which I didn't take into account.

No, the parasitic elements of the SOIC package are not the problem, although they will affect the rise time, but I have an idea of what is going on.

When the CMOS switches, it connects Vcc or Gnd to the output, so any irregularities on Gnd or Vcc get transferred to the output.  What we are seeing is Vcc or Gnd being disturbed, which is also why pre-shoot is getting through.  The solution is to reduce the impedance between Vcc and Gnd.  It might be that shoot-through currents in the output driver are ringing Vcc and Gnd.

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

I would add a ceramic and tantalum across the top of the package directly between the Vcc and Gnd pins, with some low inductance wire or copper tape.  This probably will not solve it completely, but it should improve the situation.  A better power and ground layout would be necessary to fix it, and even that won't be as good as the current based solution that I mentioned.

[shapirus]

And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling.

Yes, that creates about the shortest inductance loop you can get. The way to do it without that bodge wire is to mount the capacitor(s) on the other side of the board, right under the chip, diagonally, and use a via to route the VCC pin to that bottom side. Makes sense to use via in pad, both sides, same for the ground pin.

[David Hess]

And finally added a 1nF capacitor using that diagonal wire over the chip, to try to reduce inductance in at least some of the decoupling.

Yes, that creates about the shortest inductance loop you can get. The way to do it without that bodge wire is to mount the capacitor(s) on the other side of the board, right under the chip, diagonally, and use a via to route the VCC pin to that bottom side. Makes sense to use via in pad, both sides, same for the ground pin.

I suggested the same thing but along the top because it is not clear what access close to the supply pins is available on the bottom of the board.

I have seen dead bug and Manhattan style construction used for this circuit which had much better results, which suggests a problem with the layout.

[shapirus]

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

That's quite interesting, but:

1) it assumes that the load impedance is constant, right? Not much of a problem, though, as they are typically designed to drive a 50 ohm load anyway.

2) it's terrible in terms of energy efficiency. But only in a relative way. In absolute numbers it's probably just fine, since, again, we only need to drive 50 ohm at a low voltage, so who cares if we consume two times the power, when it still stays pretty low in absolute numbers.

But wait. Isn't that the way ECL logic works?

[shabaz]

I can try that : ) I've stuck on some copper tape, then attached the following:
100pF 0402
10nF 0603
470nF 0805
I had to piggy-back the tant, due to lack of space. It is:
TPSD107K010R0050 (100uF).

Not sure what else to try on the current PCB. I could desolder the set of capacitors attached to the red wire, since there's now better decoupling on top of the chip.

Incidentally this circuit was dead-bugged before the PCB (photo attached), and the PCB version had improved rise- and fall-times. The dead-bugging was fairly tiny, the white wires were approximately the same length to each other in the photo.
 

[shapirus]

I can try that : ) I've stuck on some copper tape, then attached the following:
100pF 0402
10nF 0603
470nF 0805
I had to piggy-back the tant, due to lack of space. It is:
TPSD107K010R0050 (100uF).

And so it's now actually worse than it was with that tiny (what was it, 0805?) 1 nF cap attached with a piece of wire diagonally?

Interesting.

What if you try it again, but this time using the same copper tape instead of the wire?

[shabaz]

Hi,
I think there was an issue with the automated measurement on the 'scope, I've switched from 4nsec per division, to 1 nsec per division in that last post, to see it closer-up. i.e. it's not got worse, but no significant improvement either. I'll grab a cature at the 4nsec/div in case it helps to compare like-with-like, since I can't go back to the earlier layout without stripping off the copper tape etc. (EDIT: 4nsec-per-div rise capture now attached).

I've attached the top and bottom PCB layers (there's nothing on the underside apart from the ground plane). It's a 1.6 mm 2-layer board.

I'm looking for a deadbug version online to compare 'scope traces with, but so far I've only found a DIP package one in a YouTube video, so it's apples to oranges. I'll keep looking.

EDIT2: I've removed the superfluous capacitors at the C2 position, and directly wired the supply (red wire) to the tantalum cap, just in case it makes a difference. No significant difference in waveform quality unfortunately  (I can capture the 'scope trace if required, but it's near-identical to the previous one).

[shabaz]

I've looked around to see if there's any waveform examples for a dead-bug version of the project, and found this link: https://www.eevblog.com/forum/projects/compact-74ac14-pulse-generator-pcb/25/
There are several projects there. There's a PCB version using a cluster of single-gate 74AUC (I couldn't see which precise part), which achieves 410 ps. The waveform looks different, and it's running off a lower voltage, it's 1.5V p-p with a 50 ohm load.

[David Hess]

I am suspicious that nothing changed.  Could there be a problem with the test setup, like the cable connection to the oscilloscope?

Better pulse generators use a different type of circuit with current switching and parallel termination instead of voltage switching and series termination, and since the current is constant, the power supply is not disturbed when switching occurs.

That's quite interesting, but:

1) it assumes that the load impedance is constant, right? Not much of a problem, though, as they are typically designed to drive a 50 ohm load anyway.

A voltage source with a 50 ohm series termination is 50 ohms.  A current source with a 50 ohms parallel termination is also 50 ohms.  They appear identical from the outside.

2) it's terrible in terms of energy efficiency. But only in a relative way. In absolute numbers it's probably just fine, since, again, we only need to drive 50 ohm at a low voltage, so who cares if we consume two times the power, when it still stays pretty low in absolute numbers.

To generate the same output from a voltage source would require doubling the voltage, so the efficiency is the same.

If efficiency is required, for lower frequency applications a 50 ohm source can be synthesized from a lower value termination resistor and some positive feedback.

But wait. Isn't that the way ECL logic works?

It is exactly how ECL works, although ECL outputs are typically buffered with an emitter follower.  An ECL pulse generator output is typically buffered with a fast low capacitance diode, but it can also be buffered with a cascode transistor.

I have thought about using a fast CMOS output to drive a cascode transistor to make a current output, but it requires a bipolar supply voltage or virtual ground so not an easy modification for you.  I should build one on some copper clad board just to see what kind of performance various common transistor cascodes would provide.

[shabaz]

Unfortunately no, I think the cable connection is very good (I've tried two cables with the 'scope, with two BNC-to-SMA adapters at the 'scope end, just in case those had an issue). Both adapters are decent (from RS and not ancient), and one SMA cable is RG-316 from RS, and the other is RG-402 (self-soldered, but I take care with that, and use it with a VNA, no issues).
The right-angle connector on the board is cheap though (LCSC I think). I could try to unsolder it (hard!) and fit a better brand connector. EDIT: I'll dremel it off tomorrow and swap with a straight connector (in case those cheap right-angle ones are no good : ( I've not used those particular ones much).
I've tried swapping 'scopes, but it's a lower-bandwidth model (500 MHz) so I can't compare like-for-like : (

[shapirus]

A related question (since it's the same pulse generator that I'm talking about). What output voltage do I actually want? Need help choosing.

To answer this... There is nothing that prevents me from making it user-selectable! I'll simply add a jumper to switch between 5 (really ~4.7) V and 3.3 V, and the problem is solved. It will also allow to compare the rise times between the two, if I ever get access to a scope that has enough bandwidth for it.

[shabaz]

I hacked off the connector with a Dremel tool, and replaced with Amphenol 132322. There's a photo  showing the connection to the 'scope, it is using a SMA-to-BNC adapter (J01008A0017).
There are attached traces using channel 1, and channel 3 on the 'scope, to see if there's any difference, but they look the same. (channel inputs are set to the full BW, 1 GHz).

I could try a different voltage (the circuit operates from 3 to 5V, but I've been using a mains-to-DC 5V brick (I could attach to an adjustable PSU; might try that at some point).

[shapirus]

so... what decoupling cap arrangement resulted in the best rise time? :)
It was a bit hard to follow all the changes and results.

[shabaz]

Hi,
Overall with the capacitor mods, there was a few percent improvement in rise-time, especially with one or more capacitor(s) on top. The additional capacitors next to the chip, i.e. soldered on the PCB, improved rise time by a few picoseconds.
Scouring the web, it seems most of the 74AC based projects are reported to be in the 500-700ps ballpark.
There's lots of interesting things to try (for instance different packages, separating out the logic into single-gates devices, adjusting delays to smooth out the current demand, and so on), but it's diminishing returns if I stick with the current circuit and PCB and trying to make tweaks to it, since the circuit is already well within that ballpark.
It depends what performance you want. As is, it's already about tenfold faster switching compared to old boatanchor HP pulse generators (of which I own one, but it covers a large portion of desk depth whenever I want to use it, and it's noisy). Another interesting thing would be to attach your circuit to (say) Pi Pico (or whatever you're comfortable with) and then you've got the ability to program pulse trains (e.g. double pulse using the Pico PIO to make it very deterministic, or specific pulse widths and so on, depending on requirements).
 

[shapirus]

Hi,
Overall with the capacitor mods, there was a few percent improvement in rise-time, especially with one or more capacitor(s) on top. The additional capacitors next to the chip, i.e. soldered on the PCB, improved rise time by a few picoseconds.

I have just realized that placing the decoupling cap across the chip diagonally (for the shortest distance between VCC and GND) is not always what is actually required to improve the output rise time.

What is the output? It's a CMOS push-pull stage, isn't it? What path does the current take when the output switches to logic high?

Must be this (considering the short time in the vicinity of the event, so we can ignore the main power rails): decoupling cap positive -> VCC pin -> OUT pin -> source impedance matching series resistor -> output connector's center pin -> coax center wire -> load -> coax shield -> ground plane -> decoupling cap negative, and the loop is complete. This current does not flow via the IC's ground pin! Inside the IC it only flows from VCC to output via the upper transistor of the output stage.

Therefore, the decoupling cap must be placed with one terminal as close to the VCC pin as possible, and with the other terminal close to the *output* pin, and connected to ground there, as that's the spot where the return current will be flowing (it's effectively a high-frequency signal, so its return current follows the signal path where it can, which is on the ground plane right under the signal trace).

Am I wrong?

Now, of course there is also the IC's own current draw, which is required to drive the gates of the output stage, and this one must indeed be decoupled with a capacitor that's placed as close as possible to both the VCC *and* GND pins to provide a low-inductance path for that. So we ideally need two caps serving different purposes.

[David Hess]

Therefore, the decoupling cap must be placed with one terminal as close to the VCC pin as possible, and with the other terminal close to the *output* pin, and connected to ground there, as that's the spot where the return current will be flowing (it's effectively a high-frequency signal, so its return current follows the signal path where it can, which is on the ground plane right under the signal trace).

Am I wrong?

No, that is right, or close enough.  The decoupling should be between the IC's Vcc and the opposite side of the load which is the coaxial ground, and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.  In practice however this will be between the Vcc and Gnd pins in your case with ground plane construction.

[shapirus]

and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.

Did you mean to say between the IC's *VEE* (the negative rail, as in dual supply op amps) and the load's ground? That would make sense, of course, if we had a dual supply situation.

Decoupling between gnd and gnd, which have the same potential and are connected via a solid ground plane (and where we don't need to block DC), doesn't sound right.

[shapirus]

Now, for the capacitance values of the decoupling caps... The project is collecting dust in the kicad directory, because I can't decide on them lol. For one thing, by parallelling different value caps, say, 2 * 18 pF (for the 250-500 ps edge) + 1 * 22 uF (for everything else), one would expect to cover all the required switching frequencies with the lowest respective impedance of the caps. But:

1) parallelling different value caps can actually make things worse than using the same number of caps of the same value because of the parallel antiresonance effect, as explained in many articles (with references to simulation and measurements to prove the point);

2) I am not sure that the consideration of matching a particular SRF to a chip switching with a duration of the edge that roughly corresponds to that frequency is even applicable. Is it? It is, when we talk about filtering, and that's demonstrated in the IN -> filter -> OUT measurements. But does it work for the case of decoupling a switching node from the power delivery network, where we need the cap to provide a very high dI/dt via the lowest inductance path possible? It seems that the inductance of lower value caps (of the same physical size) is a little bit lower, for some reason, but not that much lower, the difference can be only 15-20% or so.

The best approach here would be "try both and measure", and I'd love to do that. But what do we do when a direct measurement is not feasible?

Right now I'm thinking of doing both at the same time: use a 15-18 pF cap or two between the driver's VCC and GND to provide the small but fast transient current required to power the gates of the output transistors of the IC, and a 22 uF cap or two (following the "use the highest value in a given package you can" advice) to power the actual output -- this however still has to be fast.

[David Hess]

and then also between the IC's Gnd and the opposite side of the load which is the coaxial ground.

Did you mean to say between the IC's *VEE* (the negative rail, as in dual supply op amps) and the load's ground? That would make sense, of course, if we had a dual supply situation.

Decoupling between gnd and gnd, which have the same potential and are connected via a solid ground plane (and where we don't need to block DC), doesn't sound right.

It doesn't matter if there is a direct connection between Vee and the load, as with a ground plane, but if that was not the case, then decoupling between them will improve the situation.  The idea is to reduce the loop area from both supplies to the load for the return currents.

A single supply by itself does not guarantee that one side has a low impedance connection to the load.

[David Hess]

Right now I'm thinking of doing both at the same time: use a 15-18 pF cap or two between the driver's VCC and GND to provide the small but fast transient current required to power the gates of the output transistors of the IC, and a 22 uF cap or two (following the "use the highest value in a given package you can" advice) to power the actual output -- this however still has to be fast.

The required decoupling capacitance can be calculated from the load capacitance and allowable voltage ripple, so driving an output capacitance of 10 picofarads with 1% supply ripple requires 1000 picofarads; the capacitances form a voltage divider.  Driving a bunch of unterminated transmission lines to other logic inputs with a quad or hex package can get into the 0.01uF range or sometimes higher pretty easily.

The ESR of the big bulk decoupling capacitor provides an AC termination for the power distribution network so it may only be located where the supply input is attached.  For local regulation this is provided by the regulator's output capacitor, but there might be some advantage to placing another one at the far end of the power distribution network.

[shapirus]

Finally built. Switchable 1024 kHz / 1 kHz frequency, switchable pulse width between 50% duty cycle and adjustable value from zero (or below what my scope can capture) to 100 ns. Switchable output (or rather the VCC level of the output drivers) 4.8V / 3.3V.



Need to whack a big electrolytic on the output of MIC5205, as there's ripple on the high level output voltage at 1 kHz, 50% duty cycle, and ~500 uF of total MLCC capacity on that rail doesn't fix it: it was fine with constant load, but it's not with pulsed load. (Yes I know that MIC5205 isn't supposed to be stable with ceramic caps)

The edges are for a separate topic :).

[iMo]

MIC5205 - should not the BYP pin capacitor wired to its output (like 100pF for example) make the MIC5205's response actually faster?
Also you may try to impedance match the 12ohm (or whats ever) outputs of the CMOS drivers directly to the 50ohm connector with a pcb traces microstrip design as "the impedance transformer", without the output resistors there (the resistors have some parasitic L and C)..

[shapirus]

MIC5205 - should not the BYP pin capacitor wired to its output (like 100pF for example) make the MIC5205's response actually faster?

Hm, maybe. I didn't try this, just followed the datasheet circuit, knowing that I can, as usual, fix stability issues with a fat electrolytic cap, if necessary :).

Also you may try to impedance match the 12ohm (or whats ever) outputs of the CMOS drivers directly to the 50ohm connector with a pcb traces microstrip design as "the impedance transformer", without the output resistors there (the resistors have some parasitic L and C)..

That's an interesting idea, but I need to do my research, and that'll be a different project, maybe as an exercise in designing a 4-layer board and ordering it at a fab house. This one is done with a straightforward approach of using series resistors.

[shabaz]

Nice-looking board! And that selectable frequency is handy.
Even though I don't use the pulse generator much, it still comes in useful occasionally, as an extra signal source. I used it to test a DIY H-field probe by feeding it into a test microstrip. Also the edges are so sharp, you can use like the 101st harmonic etc., for crudely testing VHF receivers.

[shapirus]

Nice-looking board!

Thanks. And that's a handmade board! The solder mask really improves the looks of it.

And that selectable frequency is handy.
Even though I don't use the pulse generator much, it still comes in useful occasionally, as an extra signal source.

Yeah, that was the idea: make a small reasonably functional device for both learning and practical applications (which are still mostly for learning, as it's a hobby).



p.s. It emits sound at 1 kHz, 50% duty cycle output. Must be the microphonic (or rather the opposite) effect of the caps and maybe the board itself (I did VCC copper pour on the top layer). Ouch. And some instability at output high still remains, but I think I don't really care at this point. There's still room to add another 820 uF/6.3V cap, if I want to.

[shapirus]

I'm going to try to use a spectrum analyzer to estimate the edge speed of this pulser.

@tggzzz, what source of noise did you use in https://entertaininghacks.wordpress.com/2015/08/11/measuring-digital-signal-edge-rates-without-an-oscilloscope/ ? What shoud its frequency spectrum be: does it need to have uniform power distribution all the way into RF, or we only care about up to tens of MHz?

[tggzzz]

I'm going to try to use a spectrum analyzer to estimate the edge speed of this pulser.

@tggzzz, what source of noise did you use in https://entertaininghacks.wordpress.com/2015/08/11/measuring-digital-signal-edge-rates-without-an-oscilloscope/ ? What shoud its frequency spectrum be: does it need to have uniform power distribution all the way into RF, or we only care about up to tens of MHz?

Something cheap and nasty from fleabay.

The knee frequency and risetime are related as indicated. The noise source needs to have power above the knee frequency.

It is an approximate technique, and any vaguely competent noise source ought to be flat enough.

Make sure you don't overload the a spectrum analyser input; you may find a 200MHz high pass filter useful.

[shapirus]

Something cheap and nasty from fleabay.

The knee frequency and risetime are related as indicated. The noise source needs to have power above the knee frequency.

It is an approximate technique, and any vaguely competent noise source ought to be flat enough.

Yes I understand that this technique is approximate, that's why I used the word "estimate" rather than "measure".

Was wondering if my JDS2800 signal generator was suitable (it has noise as one of possible output waveforms), but apparently it won't do: its noise power nicely rolls off after 60 MHz, which, not so surprisingly, matches its max output frequency.

I'll try to find that Johnson's book for a more detailed explanation.

This is a rabbit hole indeed (but a welcome one). Since the most difficult part of creating a white noise generator seems to be finding a suitable high-frequency op amp, and it looks like I can obtain some of those locally, now I, naturally, want to try building one myself, especially now that I have an SA with which I can test its performance, rather than just buy a ready made one from Ali (even if they are sold for just $20-$25). That will likely turn out not as easy as it seems, but that's okay.

[shapirus]

Actually... aren't we just testing the max switching frequency of the IC in question this way rather than the edges speed? They are of course related, in a way, but not quite directly.

[tggzzz]

Not opamps; use RF MMIC amps.

They seem to be ~£12 on fleabay. Bg7tbl design, e.g. https://www.ebay.co.uk/itm/296127208776

[shapirus]

Not opamps; use RF MMIC amps.

Yes, figured that out already. Can probably be done with discrete RF/MW transistors as well. I think I have some, but this is something that I'll rather build using ICs. For example, found one BGA616, seems to be suitable and can be had locally for about $1.5 apiece.

They seem to be ~£12 on fleabay. Bg7tbl design, e.g. https://www.ebay.co.uk/itm/296127208776

Ebay doesn't ship to Ukraine now, but that same stuff can be bought on Aliexpress. But price is not the point. $25 vs £12 or whatever makes no difference: I want to build the thing myself now, as it seems to be a perfect little project for experimenting with: cheap, simple in theory, low component count, easily measurable performance.