Bus conflict between 6502 and STM32

[Jaunedeau]

Hi,

  I am trying to make some peripheral using a bluepill (STM32F103) for a computer on which the adress and data bus (but not the R/W nor clock signals) are available on the cartridge port.

  The 6502 is a MOS one, according to this datasheet it used "N channel, silicone gate, depletion load technology".

  I want to avoid problems in case a bug in my code is causing conflict on the databus where both the STM32 and the 6502 are making write access.

  If I understood correctly, the 6502 can draw a lot of current when pulling the signal to LOW, but won't source much to try going to HIGH. Then I deduce that if I only configure the GPIO linked to the databus to either input or open drain and not push-pull, even if a bus conflict happens I would just AND the values on the databus (if either the 6502 or the STM32 tries to output a zero, zero it will be).

  Is that a safe assumption ? Will I need to add some (high value) pull up resistors if I configure the STM32 in open drain instead of push-pull ?
  Could I also :
- configure pins as open drain
- activate the pull-ups for input mode on all pins
- write 0 to the gpio port (set all output as 0s)
- only configure as output the pins I want to write to 0, letting the other as input and benefit of the STM32's pull ups resistors ?

Thanks,
j.

[KrudyZ]

Sounds like this cartridge is meant to be a ROM only.
The processor supplies an address and the cartridge replies with the data for that address.
It's a bit odd that there would be no read enable line to tri-state the bus, but maybe the bus isolation is built into the computer to make the cartridges as cheap as possible.

[Jaunedeau]

The cartridge port was first intended to be ROM, but later cartridge including bankswitching and RAM. The atari 2600 is the one I'm using as reference but I know other did.

[iMo]

Mind the 6502 is a 5V i/o device, afaik, the stm32 is a 3.3V i/o device.

[Jaunedeau]

I have (just) enough 5V tolerant pins on the stm32f102 for my need, and the 6502 specifies a Vih for logic with a minimum of Vss + 2.4V. Of course I'm not 100% sure that will work (there might be sont speed issues, ...) but I can make tests as long as I'm confident not to fry the 6502 (or other components writting to the databus) with a bus collision.

[SeanB]

Simplest is to put a series resistor of 22R on all those lines, which will still allow the CMOS inputs to be driven, and which will limit the current otherwise, so no damage to the outputs driving each other. Exactly what you see on high speed memory buses to keep reflections low, and to handle the slight chance of one chip still driving the line while another is busy getting data out during a read, as they run overlapped access cycles.