how do i parallel n channel power mosfets together for higher Current rating

[donald]

 

I have few Mitsubishi "FS10UM-12" on hand and wanting know if N-Channel Mosfet can be paralleled together and how would i go about doing it, I would love know how they work together ,to make higher current rating?? I am trying design my own dc P/S load checker and are there any gap difference instead using bipolar transistor ie 2n3055/2n2955 ..



don

[madires]

IR got a nice paper: www.irf.com/technical-info/appnotes/an-941.pdf

[David_AVD]

In audio amplifiers with FETs for the output devices I've often seen the sources and drains in parallel.  The gates all had a separate "stopper" series resistor.

Don't FETs have a negative temperature coefficient and tend to share current pretty well anyway?

[Smokey]

This is a great appnote.  It's sparse on details, but gives a great overview.  Should get you started.

http://www.microsemi.com/sites/default/files/micnotes/APT0002.pdf

ps... the best answer is you need to match the FETs.

[David_AVD]

In audio amplifiers with FETs for the output devices I've often seen the sources and drains in parallel.  The gates all had a separate "stopper" series resistor.

Don't FETs have a negative temperature coefficient and tend to share current pretty well anyway?

That works well when they're fully on. Then as the temp increses in one the current through it decreses. He wants to use them in an electronic load though. When you use them like that each one will have a different Vgs for a given Ids. Best way is just to use opamp per fet.

That's interesting as I've seen it in class AB audio amplifiers where the output devices are never fully on.  I agree that you'd still want to use FETs that are reasonably matched to start with.

[Psi]

I've taken apart many hobby king RC plane speed controllers.
They have 6 mosfet banks (one for each of the 3 phases plus the high and low parts of the hbridge) and between 3 and 10 fets in parallel for each.

The drains and sources are directly in parallel but the gates for each have a 100R resistor to the fet driver IC.

I'm not saying its the right way to do it, just that it works fine for cheap china products.
They switch between 20 and 100A depending on model.

http://www.etotheipiplusone.net/pics/kewlmoter/hk_18_esc_5.jpg

[Psi]

I edited my post, as there is 3x2 banks (forgot about the half bridge sections)

They're used as switches to generate a 2phase square wave which alternates around all 3 motor phases while using the unused one for feedback.

Found a circuit diagram for a small ESC. It looks to have banks of 2 fets in parallel.
The larger ESC's have a dedicated gate driver but this one just has transistors

http://i57.photobucket.com/albums/g236/kratchouf/TowerPro25aEscSchematic.png

[donald]

  OK don't even bother describe how reply each post...

OK this i suppose would be linear design where max voltage be 12V and as each mosfet (FS10UM-16) --> www.datasheetcatalog.org/datasheet/powerex/FS10UM-12.pdf

to able withstand 30A , but after sum reading    u should allow 20% of efficient use,  of mosfet.

maybe time i go my junk box and try find better mosfet that can carry larger ampere.. i was hoping not using any op-amp as best i have lm324 ..

don

[poorchava]

This is a great appnote.  It's sparse on details, but gives a great overview.  Should get you started.

http://www.microsemi.com/sites/default/files/micnotes/APT0002.pdf

ps... the best answer is you need to match the FETs.

Dafuq.... 120 kW electronic load  . I want that

[Nic]

I built a PWM motor controller at 24V and I parallel three mosfet IRF1404, each 162A current 4m? RDs ON resistance, 200W. How can I calculate the max current or power in Watts of the system output?
 Should I suppose that Imax= 3 x 162A or Pmax= 3 x 200W or nothing of that?
Please help

[madires]

I built a PWM motor controller at 24V and I parallel three mosfet IRF1404, each 162A current 4m? RDs ON resistance, 200W. How can I calculate the max current or power in Watts of the system output?
 Should I suppose that Imax= 3 x 162A or Pmax= 3 x 200W or nothing of that?

Don't believe the marketing department! First you have to find out how much total resistance the MOSFET has, including leads and everything, then consider the thermal design and the PCB (traces, connectors). The whole package determines the output power.

[fivefish]

  I parallel three mosfet IRF1404....... Should I suppose that Imax= 3 x 162A or Pmax= 3 x 200W or nothing of that?

It's not that simple.... you need to look at the SOA graph.

Yeah, that MOSFET will do 200A according to page 1 of datasheet, but only in certain condition.
Look at the graph.



See the 200A on the Y axis? Look at the voltage... somewhere between less than 2.0V

Then it's down to 30A around 10Volts, and less than 10A around 40V.

If you exceed these ratings, after a few seconds, your MOSFET goes shorted Drain-to-Source.

[digsys]

Yeah, that MOSFET will do 200A according to page 1 of datasheet, but only in certain condition.  Look at the graph.
If you exceed these ratings, after a few seconds, your MOSFET goes shorted Drain-to-Source. 

+1
I've run controlled destructive testing on 100s FETs, to guarantee product reliability. ONE thing I can tell you for sure is - the graphs LIE !
Most the time, they are 20-50% over-stated and up to 100%. There is NO standard test methodology for SOA, each manufacturer makes up his own.
Even on a TO247 package with the highest grade insulator, I've never had >1sec before destruction. AND you need to read up on hot-spotting as well !!
eg You may calculate a SOA 8A at 50V, but it'll be 6A or 5A in reality. ALSO NOTE, once in SOA, you switch from PTC to NTC !! SO you get thermal runaway !
There are a few types specifically made for linear operation eg IXYS
This paper is an excellent start - ntrs.nasa.gov/archive/nasa/casi.ntrs.nasa.gov/20100014777.pdf

[fivefish]

Don't forget temperature limits also, and effects of rising temperature.
Exceeding the temperature limits (not enough heatsinking, not enough forced air cooling) causes MOSFET breakdown way before the edges of the SOA specs are reached.