I guess I was referring to this:
http://www.tuxgraphics.com/electronics/200707/bench-power-supply-unit.shtmlThey use ATmega8 which has maximum ADC sampling frequency of around 15kHz for full 10-bit resolution (at 200kHz ADC clock, single-ended free running mode, 13 ADC clocks/converison). And they do two ADC converions per loop (current and voltage).
That would put the maximum control loop frequency at around 7.5kHz, or 133us per loop, at best.
Now why this seems slow to me is that in
L7805 datasheet from ST there is a graph of transient response that looks like it takes somewhere around 5us for the whole regulation to happen after a step load change...
Maybe they run the ADC over the spec (you can do it but lose LSBs...)? Minimum conversion time is stated as 13us in the datasheet, that is at maximum 1MHz ADC clock, and that is at like 7 bit accuracy at best according to datasheet... 26us per loop. Still not close to 5us reaction time of a linear regulator (and that is just how long it takes for the regulator to notice it has to do something, it does not take into account any actual stabilization AFTER the DAC has been updated to compensate...)
EDIT:
I have checked the actual project sources, it runs on 4MHz cpu clock with 1/32 divider = 125kHz ADC clock = 9615 Hz sample rate, resulting in 208us loop. Even slower than i thought.