Author Topic: Gate protection on a P-channel MOSFET  (Read 6212 times)

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Offline davebkcTopic starter

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Gate protection on a P-channel MOSFET
« on: November 06, 2015, 01:14:47 am »
Hi all,
There a plenty of examples on the Internet for protecting the gate of an n-channel MOSFET.  Can someone help me understand how I would do the same for a p-channel? 

The circuit in question is below.  I've destroyed the mosfet in the first stage a couple of times now and would like to fix the issue once and for all. And yes, I'm sort of assuming ESD is the culprit here. 

Thanks,
Dave
 

Offline forrestc

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Re: Gate protection on a P-channel MOSFET
« Reply #1 on: November 06, 2015, 07:21:13 am »
There a plenty of examples on the Internet for protecting the gate of an n-channel MOSFET.  Can someone help me understand how I would do the same for a p-channel? 

Pretty much the same as a N channel.   My preference is to stick a TVS protection diode between gate and source.  Looks like the Vgs of the BS250 is +-25V.   Pick something a fair bit lower than that.  Since the

 

Offline mij59

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Re: Gate protection on a P-channel MOSFET
« Reply #2 on: November 06, 2015, 07:41:02 am »
A 12V zener diode connected between gate and source should be enough.
If the mosfet is damaged by a high input voltage, try clamping the input voltage e.g. with a zener diode or tvs
 

Offline T3sl4co1l

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Re: Gate protection on a P-channel MOSFET
« Reply #3 on: November 06, 2015, 09:11:12 am »
For even more protection, add a series 10k resistor to the gate, and put a zener on each side (to GND).  This accounts for the first one not doing its job, e.g. due to stray inductance (ESD sparks are incredibly fast, enough even to destroy a gate that's apparently shorted to ground, because of the stray inductance of the short!).

Also, why P-channel in the first place?  There's nothing special about them, the physics are exactly identical to N-channel.  No difference in distortion, and, not really a difference in price or availability because BS250 isn't going away any time soon.  It's just perversity for the sake of perversity.  A trait that's sadly all too common in audio design...

Tim
« Last Edit: November 06, 2015, 09:13:24 am by T3sl4co1l »
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Offline davebkcTopic starter

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Re: Gate protection on a P-channel MOSFET
« Reply #4 on: November 06, 2015, 06:19:46 pm »
It might have helped if I'd mentioned that:
1) This is a high-gain distortion circuit that sits between an electric guitar and an amplifier. 
2) The circuit was originally drawn with a positive ground and -9v supply (I modified it below to try to understand better). 

There is an n-channel version of the circuit but without investigating the "why's," the word in the guitar effects community is that this p-channel version is the preferred circuit as it's considerably quieter.

With all that said, I'm still confused about what direction to install a TVS/zener.  It appears to me that it needs to be installed backwards compared to a conducting LED.  Is that because it's supposed to do nothing until a the gate exceeds the source by the (let's say) 12v?  If that happens (and assuming I've drawn it correctly), the current flow is what's confusing me. 

Thanks for your patience.   :)



 

Offline T3sl4co1l

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Re: Gate protection on a P-channel MOSFET
« Reply #5 on: November 06, 2015, 10:22:56 pm »
Yes, that's the correct direction and connection. :)

If quietness is desired, a low noise front end would be better suited (perhaps using a JFET, or BJT if the impedance is lower).  MOSFETs are notoriously noisy -- and again, this doesn't depend on polarity, only device type, geometry, and circuit design.

Noise is better addressed by using many devices in parallel (the statistics work out in your favor), probably running the total circuit at a rather wasteful bias current.  Only the first stage needs to be like this.

With so much gain, it's going to be noisy, anyway.  That's simply the nature of any clipping circuit.  You could create one that's biased in such a way that it has low gain when there's nothing around, but it would have a significantly harsher sound, and would lose whatever sustain gets buried in that cutoff region.  (Namely, this would be a class C push-pull amplifier: it goes from cutoff (little gain) to linear operation (high gain) to clipping (low gain again), over the span of the waveform itself.)

A more subtle approach might shift the bias, effectively acting as a squelch circuit or noise gate.  When the amplitude is low, bias is low; when amplitude is normal, bias (and therefore gain) is high.  But this is also the definition of an expander, so will again screw with the sustain and timbre.

If it's any consolation, you get the same noise limitation if it were a digital stomp box, because the noise is ultimately coming from the source.  Some very complex digital methods could help (spectral analysis, signal detection, noise filtering, etc.), but that takes more effort than I would expect (but hey, a top-of-the-line model might offer such).

Tim
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Offline John Coloccia

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Re: Gate protection on a P-channel MOSFET
« Reply #6 on: November 06, 2015, 11:03:45 pm »
The reason people use MOSFET (other than how they sound when they clip, which is a whole other can of worms) is to get the high impedance input. JFets can be a pain in the butt because you either have to sort them or include a trimmer to get them biased properly. A good compromise is a JFet opamp for the buffer, like a TL072. There are some quieter ones I tracked down, but they're very expensive and difficult to get if you're not buying in quantity.

At least that particular design isn't going to crackle when you turn the gain knob.  ::)
 

Offline T3sl4co1l

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Re: Gate protection on a P-channel MOSFET
« Reply #7 on: November 07, 2015, 12:12:29 am »
Well, MOSFETs aren't very much better sorted (BS250 Vgs(th) -1 to -2.4V).  Again, physics... to a certain extent.  FETs are FETs, though within a broader meaning this time (Vgs(th) varies over a relatively wide range for both kinds, though for different reasons).

Using JFETs here would amount to removing the positive gate bias resistor, and probably adjusting the source resistor.  Yes, variable or selected resistance would help, since Vgs(th) still has a wider range on most types.

For low noise applications, matching isn't really necessary, for the properly spec'd types (e.g., 8-20mA -- not the pitiful 2-20mA range you get on floor sweepings like the 2N3819!), and your results may be even better than expected if they happened to come from the same lot, or wafer.  (The noise reduction goes by statistics on Gm, which is about proportional to Idss.  If you run them at Idss, the ~2:1 Gm spread is only a sqrt(2) spread in statistical weight, still enough to care about, at least until you have, like, 6 or 8 in parallel.)

If you're going to kind of give up and use an op-amp, the excess noise is probably about what you'd get from a discrete MOSFET, so not a big deal either way -- if you have the op-amps on hand, who cares?

That said, there are some quite good JFET op-amps available (if you don't mind shopping for them), which will surely beat discrete MOS, and probably even a crummy JFET stage too.  Which is pretty cool, considering op-amps have on the order of 100 active transistors in them, these days.

Changing just the first stage is nice, because that has the most impact on noise floor while making the least on distortion response, except for the very strongest of input signals.

Tim
Seven Transistor Labs, LLC
Electronic design, from concept to prototype.
Bringing a project to life?  Send me a message!
 

Online Ian.M

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Re: Gate protection on a P-channel MOSFET
« Reply #8 on: November 07, 2015, 12:57:07 am »
The problem with adding the obvious clamping Zener is reverse leakage current.  The biassing resistor divider for the first transistor has a standing current of ~1.9uA.  The clamping diode leakage needs to be at least an order of magnitude less.  You also have the Zener junction capacitance in conjunction with the added protection resistor that needs tp be in series with the input signal rolling off the HF response.  Fortunately running the worst case numbers for a BZX55 series diode and a 10K input resistor give a corner frequency up around 90KHz, and this aint audiiophool HiFi so that will be fine.

However you can virtually eliminate the problem of Zener leakage affecting the bias if you move the clamping (and the input protection resistor) to the input side of the input coupling capacitor.  You'd need two identical Zeners in series there across that 1.5M resistor that's supposed to discharge any static, with the Zeners in opposite directions so both negative and positive spikes get clamped.
 

Offline davebkcTopic starter

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Re: Gate protection on a P-channel MOSFET
« Reply #9 on: January 04, 2016, 04:31:14 am »
Well, MOSFETs aren't very much better sorted (BS250 Vgs(th) -1 to -2.4V).  Again, physics... to a certain extent.  FETs are FETs, though within a broader meaning this time (Vgs(th) varies over a relatively wide range for both kinds, though for different reasons).
And to that point, the author recommends breadboarding the circuit first to correctly set the bias:
"It's important to build the circuit on a breadboard first, as the MOSFETs will usually require re-biasing. Adjust the 3.9k resistors until the drains are at approximately 4.5v. This doesn't have to be exact, anywhere between 4-5 volts is fine."

http://www.diystompboxes.com/analogalchemy/sch/obsidian.html

Thanks for the help and sorry for the delayed response (I got obsessed with building the ultimate sawhorses and I work very slowly   :) )
 


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