Perhaps, but I'm still not convinced. I looked at the 24C64 data sheet it lists the pinout as follows: 1: A0, 2: A1, 3:A2, 4:GND, 5:SDA, 6:SCL, 7:WP, 8:VCC.
From the image I see C172 is the decoupling cap so we can assume pin 8 is indeed VCC. Pins 1 to 4 seem tyo be connected together so we can assume thats GND and the A0,A1,A2 pins are 0 the standard configuration. We could also go one step futher and assume R42,R41,R40 are the pull-ups for pins 5,6 and 7. So everything sounds good, but why do we have a pull-up on pin 7 which would be WP, this is normally tied to VCC or GND.. and even if the main processor was using that for write protection.. why the pull-up? perhaps so its write protected and then the processor pulls to GND when it chooses to write to the device? I suppose that's feasible.
I'll have my friend test it out and see if we can read the EEPROM. I'll post a response with details.
Thanks.