How is transistor gain determined?

[simpson]

How do manufacturers determine the gain of a particular transistor design?

[SeanB]

They don't. It is determined by things like the device geometry, the thickness of the diffusion layers, the current used in testing, temperature and such. That is why you typically get a range that can vary from eg 50 to 500, with a typical value of 180. If you want a more closely defined gain then you can buy devices that have been selected to either fall within a smaller range or you can buy matched devices, which will track each other more closely.

The variation with current is very large, if you look at a power device it might spec a gain of 50 at low current ( perhaps at 10V across collector and emitter, with 100mA flowing) and go as low as 1 or even 0.8 at 15A with 5V across collector and emitter. Same device, and operating just with different current densities. Yes, the device with 0.8 gain is still a usable device.

[retrolefty]

The spec is a guarantee that the device's gain will be somewhere between the min and max stated in the conditions given in the datasheet. Stage gain should be designed/set with external components for any 'analog' stage, not relying on the devices gain value. For switching applications it's not a real factor as you tend to drive the device into saturation anyway.
 

[T3sl4co1l]

They do.  By simulation.  Then by experimental qualification (prototype die testing), and finally by measuring packaged parts.

There are tools out there, probably mostly insanely closed-source, sign-ten-NDAs-and-deposit-$10k-please-and-we'll-send-you-just-the-brochure sorts of things, but they do indeed conduct true semiconductor physics simulations (and probably multiphysics, where relevant -- some power and RF applications including thermal gradients or magnetic fields).  They can measure and model, not only the in-circuit terminal characteristics, but the properties at every point within the device, including current density, carrier density, power density, charge balance, electric field, etc.

As for what the board-level designer has... that's pretty much SPICE.

If you've poked around much in a SPICE simulator, you'll see weird constants like gate oxide thickness (TOX), channel length, width, junction area, etc., which go into some of the models, and do indeed correspond to certain attributes of geometries that were typical at the time.  (We're talking 70s-80s tech here.  Ancient stuff!)  None of the quantities are *quite* what their names suggest (especially the geometry-dependent ones, like the 'channel sidewall' stuff, which really just serve as a corrective hack to tweak expected geometries), but they're close enough to count as "physics based models", at least for the given subset of "physics" they relate to.

Tim

[free_electron]

layer thicknesses, doping strengths and geometries.  it can be simulated and there are tools for that ( no not in the 10K range... needs a couple more trailing zeroes ... )