How to design with CMOS inverter amplifiers

[Infraviolet]

Ok, so a while ago someone on here suggested to me a trick (sorry, can't remember who, but thank you, it looks like it can be a very useful trick to me)  for amplification of signals too fast for the op amps I had to hand by using a 74HCU04 (or other UNBUFFERED NOT gate chips) in a linear mode.

This involves coupling a capacitor from the signal source to one end of an input resistor, the other end of the input resistor goes to the NOT gate's input, a feedback resistor then runs from the gate's input pin to its output, and the output can then, either with capacitive coupling*, or directly*, be used to provide higher voltage signals to further circuit elements.

*some descriptions seem to show the capacitor on the output, others don't I certainly didn't seem much effect when having it there versus replaced by just a wire, both when the amplifier's final output was driving just an o-scope probe (10Mohm, <12pF), and when it was driving in to a 1K resistor to ground as well as the scope probe. Is there a reason they show it, if one is driving a second stage of CMOS inverter amplification then surely one only needs the coupling capacitor input one would already fit it with if it were acting independently, no need for an extra coupling cap?

National Semiconductor's AN-88 app note covers this concept "CMOS Linear Applications" briefly.

I've been giving it a go and found some odd things and wanted to understand a bit more, but don't know where I can get further info, because AN-88 doesn't say a vast amount (even so much as not giving the equations and full captions you'd expect for its figures), and google searching didn't find me that many full answers, just discussions. This https://wiki.analog.com/university/courses/electronics/electronics-lab-20 also covers some stuff, but not enough either.

I had thought the ratio of the input and feedback resistors will equal the gain, roughly, but I'm finding things very diferent. For a 3MHz sine signal  input(500mV peak to peak) with a 5V and ground power supply for the inverter chip I'm needing resistor ratios of 10s to get gains of 3. I'm also finding things don't seem to depend solely on the ratio, a larger pair of resistors with the same ratio doesn'tgive the same gain, not even close, as a smaller pair. A 1K input and 10K feedback gives a gain of around 3, whereas a 10K input and 100K feedback gives a gain less than 1.

Is there a clear equation governing the gain of a CMOS inverter amplifier, ignoring circumstances where one is trying to gain something to the extent it would come very close to the rail?

Is there some sort of "slew rate" like thing going on here, perhaps controlled by the absolute sizes of the resistances rather than their ratios, where gain is limited for a signal at a particular speed?

Then when I stacked up two CMOS inverter amplifiers with one feeding the input of the next, keeping the coupling capacitors an input resistors so each alone was just the same circuit as a single one acting alone would be, I got a gain from the pair much greater than the product of the gains either had given when used alone.

Are they interacting with each other in some manner, or does the output of one provide some input impedance effect to the next stage despite having an input resistor present?

And I had expected that when the input and feedback resistors were equal I'd get a gain of 1, but instead I found a gain much less than 1, again varying with how big the resistors actually were. Yet when putting two such amplifiers in sequence, the first with a large enough ratio to give a gain and the second with a 1:1 ratio, the final output was nonetheless larger than the gain of just the first stage alone.

Trying to work out empirical equations for whatever is going on would require varying an awful lot of independent parameters it seems, resistance sizes as well as ratios, amplifiers in sequence and alone...

Another thing I found was that within a single chip, I could run two amplifier stage just fine, but if I tried three amplifier stages  then I got a much higher frequency signal(15 to 20MHz maybe) superimposed on the waveform, and when the input signal was weak and one would expect the output to be sitting at close to 2.5V and nearly flat, I instead got this high frequency waveform becoming dominant.

I'm also a bit unsure about the maximum number of elements in the hex chip one should use, a single gate acting in this manner, with the others all grounded on their inputs, has the chip comsuming about 12mA. There is an abs max figure given in most 74HCU04 datasheets of 50mA for the whole chip, and 25mA per channel, but no recommend long term operating maximum. Does this mean I'm ok to run up to 4 gates in this fashion, 4x12<50, or is there a further percentage by which I should try to work below the abs-max current draw? The chip (DIP in breadboard testing, SOIC in my final application) doesn't have any obvious pad for heatsinking if I ought to do that, but I could make the ground and power planes/traces near the chip's suppply pins big with lots of vias if that would be wise?

Can anyone point to resources that give the full details on how to make use of this "Unbuffered CMOS NOT GATE as amplifier" trick, particularly an equation to let one select the most appropriate resistors for a desired gain rather than having to trial-and-error it.

Thank you

[Benta]

You're applying "op-amp" rules to this, where a CMOS inverter actually has a voltage gain of perhaps 3 or 5 or 7 (undefined).
Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

[Infraviolet]

Yes, this is on a solderless breadboard, I know they have issues but it is quicker to test ideas on one than get an actual PCB made for soldering to, or work with stripboard.

If we ignore the strange situation with those fast oscillations, is there an equation for the gain versus the resistances?

[mawyatt]

We've used CMOS Logic Gates as analog amplifiers and limiters since RCA first introduced the CD4000 series way back around 1970. As Benta indicated you can't treat these as infinite gain op-amps, however if you do a little analysis assuming a finite gain G and a high input Z and low output Z CMOS gate you can estimate the closed loop gain as -{(Rf/Ri)G/((Rf/Ri)+1+G)}, where Rf and Ri are much smaller than the CMOS input Z and larger than the CMOS output Z, and G is the Open loop ~ midpoint (VDD/2) CMOS Gate small signal gain magnitude.

 With G ~ infinity then the gain becomes -Rf/Ri as expected!! With an Rf/Ri ratio of 10, and G ~ 5, ones aspects a closed loop gain of -3.125.

A little more involved in the details of the internals one finds they are not symmetrical as assumed, the PMOS is weaker than the NMOS. You can observe this by simply shorting the input and output and measuring the resultant DC voltage, it's not exactly VDD/2 as a symmetrical structure would produce. If you look or plot the static transfer (Vo/Vi) you will see a nice smooth compression at the extremes like a soft slanted stretched "S", which can be quite useful in analog signal processing.

BTW you can get the Gain G by taking the slope of the transfer curve around the center VDD/2 point, it's simply (delta Vo)/(delta Vin).

Best,

[tggzzz]

You're applying "op-amp" rules to this, where a CMOS inverter actually has a voltage gain of perhaps 3 or 5 or 7 (undefined).
Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

Beat me to it!

Yes, this is on a solderless breadboard, I know they have issues but it is quicker to test ideas on one than get an actual PCB made for soldering to, or work with stripboard.

Does that "quicker" include the time spent wondering what's happening, writing your post, waiting for responses and responding to them?

The speed of inserting components is an irrelevant metric; what matters is the time to getting a working circuit (or knowing why it cannot work).

You should understand why manhattan techniques enable you to easily and speedily get good electrical behaviour and results.

FFI see examples in the latter part of https://entertaininghacks.wordpress.com/2020/07/22/prototyping-circuits-easy-cheap-fast-reliable-techniques/

Engineering maxim: it is faster to "do it right2 than it is to "do it over".

[Infraviolet]

Mawyatt, thank you very much indeed for that equation. I'll do some more tests and see how well it applies to them.

Closed_loop_gain= ( Rf/Ri )G  / ( (Rf/Ri)+1+G )

[glarsson]

Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

We experimented with CMOS inverter amplifiers in 1977 using a solderless breadboard.  At power on it oscillated in the FM broadcast band, so clearly it didn't work as an amplifier. It produced a carrier detectable over 100 meters away. 

[tggzzz]

Your spurious oscillations are more likely layout/decoupling related.
Are you one of the poor souls that use "solderless breadboards"? Aka "where's the garbage bin?"

We experimented with CMOS inverter amplifiers in 1977 using a solderless breadboard.  At power on it oscillated in the FM broadcast band, so clearly it didn't work as an amplifier. It produced a carrier detectable over 100 meters away. 

If it oscillated, it must have worked as an amplifier!

[glarsson]

If it oscillated, it must have worked as an amplifier!

Ok. It couldn't be used as an amplifier.

[Infraviolet]

From what I've heard that sort of extreme oscillation happens if you try to use unbuffered NOT gates in this manner. I haven't had anything like that with the 74HCU04. That weird oscillation I saw (more like 15MHz than 100MHz) only occured when I used several gates at once in one chip, I'm doing some more breadboard tests today to establish one or two more things before I get PCBs ordered.

[Zero999]

You built it on a breadboard, so have a nice LC oscillator.

Just one question: why? The usual reasons for using a logic gate in its linear region is to make an oscillator, or boost a low level signal up to make a nice square wave. In other words, logic gates are not typically used to amplify a signal to give a nice linear output. That's the domain of op-amps. Logic gates are inherently non-linear. The gain varies depending on the output voltage. It's always higher, when the output voltage is closer to half the supply voltage because the MOSFETs are biased more into their transconductance regions.

[T3sl4co1l]

Don't pay much attention to the poopers poo-pooing breadboards.

Just remember, as is the case anywhere, lead length and dress matters.

Don't use those goofy ten inch premade crimp pin jumper kits.  Cut your own from solid wire, flat to the board or in short arcs.
Mind the effect of capacitance between slots (typically ~4pF).
Mind the effect of basically not ever having ground plane.  You rely on wiring and supply buses (just more wires, they're only strips embedded in the board) for ground quality.
All of these effects can be quantified and accounted for, between theory and practice.

3MHz is not extreme for a breadboard, but you do need to be careful with it.

The main thing is, a random circuit, build on breadboard, with random (as yet undefined -- we need to know before we can tell!) materials and parts, is more likely to perform badly, while a random circuit, built on PCB, is more likely to perform well.  There is no guarantee that either will perform correctly at all.  Only once both are fully defined: that is, including the length and placement of wires, components, etc., and nearby / surrounding / supporting metal (preferably, build your PCB with a ground plane; for the breadboard, mount it on a metal plate and wire that to circuit common/GND), can operation be reasonably anticipated.

I'm quite serious -- get out a ruler and measure the length of those jumpers!  Length matters, because signals propagate at the speed of light, and the in-circuit consequence of that is some capacitance which loads the signal, and inductance acting in series along the wire.  It's a rate of roughly 1 nH/mm.  So those 10" jumpers or whatever they usually are, add up quite quickly (~200nH?) when you're taking MHz signals.

Not to mention, where jumpers make large sweeping arcs amongst each other, there's comparable mutual inductance between them (affecting signal or power quality further, or providing feedback for high-frequency oscillation).  Short links have less mutual inductance to each other, better compartmentalizing sections of the circuit.

Tim

[MK14]

I don't know if the OP, has seen this.  It seems to go into a lot of details, about this amplification technique.

[tggzzz]

...
3MHz is not extreme for a breadboard, but you do need to be careful with it.

The main thing is, a random circuit, build on breadboard, with random (as yet undefined -- we need to know before we can tell!) materials and parts, is more likely to perform badly, while a random circuit, built on PCB, is more likely to perform well.  There is no guarantee that either will perform correctly at all.  Only once both are fully defined: that is, including the length and placement of wires, components, etc., and nearby / surrounding / supporting metal (preferably, build your PCB with a ground plane; for the breadboard, mount it on a metal plate and wire that to circuit common/GND), can operation be reasonably anticipated.

tpd is 6ns, so gain at >>3MHz.

Other construction techniques have a better chance of success; manhattan on a solid groundplane is much better.

I'm quite serious -- get out a ruler and measure the length of those jumpers!  Length matters, because signals propagate at the speed of light, and the in-circuit consequence of that is some capacitance which loads the signal, and inductance acting in series along the wire.  It's a rate of roughly 1 nH/mm.  So those 10" jumpers or whatever they usually are, add up quite quickly (~200nH?) when you're taking MHz signals.

Not to mention, where jumpers make large sweeping arcs amongst each other, there's comparable mutual inductance between them (affecting signal or power quality further, or providing feedback for high-frequency oscillation).  Short links have less mutual inductance to each other, better compartmentalizing sections of the circuit.

Having a look at the datasheet https://www.ti.com/lit/gpn/cd74hcu04 indicates that when an input is at Vcc/2, then the current is ~15mA and the input capacitance is 40pF. The current  falls off fast as the input moves away from Vcc/2.

All that means a surprisingly high (cf opamps) current change, a relatively high (cf logic levels) capacitance, and probably relatively long lead inductance. That's all a recipe for unintended behaviour in a lazily/ constructed circuit.

A simple spice simulation of a current step into a 40pF capacitor and a realistic inductance (200nH?) should yield useful insights as to the potential for oscillation.

[T3sl4co1l]

For reference, I've breadboarded amplifiers and switching circuits using 2N3904s and friends (fT ~ 300MHz) before.  Which go almost as fast, and at comparable bias currents (10mA).  Oscillation isn't at all guaranteed there, either, but keep in mind that might be a single transistor, or few at a time, not an array of six pairs.

In contrast, I once breadboarded a Z80-CPU and a handful of other things, and that, just running at 4MHz (yes yes, implied edge rate some times higher, but it's "only" NMOS, fairly weak drive strength; the TTL bus latches (output ports for blinkenlites) were probably the worst offenders; also being that one had an LED display matrix on ribbon cable hanging off it, heh.  It worked fine for the most part, but would crash randomly -- or not really "random", but also "perfectly" randomly, in that it was reliable/consistent (weeks of uptime blinking out a set pattern) in an earlier version, but a later version I added an LFSR noise generator, after which it might run a day or a week between crashes.  (And it would crash-crash, because it was the NMOS CPU; clock bounces or stops momentarily or whatever it was reading that upset it, and that's it, it's toast, internal state is lost, reset required.  Well maybe CMOS would crash too, I don't know, if it were a fast double-tap, that could corrupt it just as well.  But those are my assumptions anyway.  No way to tell, and actual cause doesn't matter anyway; obviously it's a marginal signal quality issue caused by the breadboard.)

The worst of both worlds, however, was one time I tried breadboarding a -- I think it might've been a type-T flip-flop in ECL/CML?  That most definitely did NOT work: too many transistors, too much gain, it oscillated between stages -- at some 100MHz or so, which is a frequency consistent with lead lengths / propagation delays along such a chain, and node capacitances and all that.  (I eventually later built a variant of that circuit Manhattan-style, which worked beautifully.  It's a rather pleasing circuit, in terms of topology and construction, and might make a good project to investigate and build, if I might so humbly suggest. )

Yet another example, of more direct application / reference here, was one time where I had a ATMEGA32 breadboarded, and wired to an analog (ADC/DAC) board I had put together -- this on ground plane, hand carved / Manhattan style, with SPI leads going back to the breadboard.  Well, those fly leads were a good 10" or so long, and, you guessed it, the data was crap.  Put a ferrite bead on SCK and SDI/O, added a couple more ground wires -- no problem, solid data, reliable readings.  (Which was at a time when I "knew what I was doing", so the problem was easily recognized, verified (there was significant ringing on the signals) and addressed.)  ATMEGA isn't particularly fast (it's 5V CMOS, roughly 74HC scale I think?), but I just wasn't sure if it was fast enough to be a problem here, and it turns out it was -- good to know.

So, the stability, the coupling and risk of oscillation, the general noise levels, all of it gets worse with scale.  Telling someone they can't do a single-gate oscillator or amplifier this way?  Come on, that's BS and y'all know it.  It needs to be done carefully, and let's say might be a good learning opportunity in seeing how wire length matters -- as long as one is aware of the effect, and has the commitment to play around enough to tell -- it does take some effort to replug the circuit, making sure unused gates are tied off, supplies are wired short and well bypassed, signal lines are short and low, etc.  Conversely, if you're not interested in that kind of exploration -- maybe keep it to simpler things, like single transistors, and low bias currents where they don't sing, or add a ferrite bead around the base lead to kill any possibility of it trying.

Tim

[RoGeorge]

If you look or plot the static transfer (Vo/Vi) you will see a nice smooth compression at the extremes like a soft slanted stretched "S", which can be quite useful in analog signal processing.

Such a sigmoid-like function should also work well for making an artificial neuron out of a CMOS gate. 

The coefficients of the neural network (NN) can be calculated on a computer at first.  Once the NN was trained on the computer, then the calculated coefficients can be implemented in hardware, as summing resistors at the input of each gate, a resistor for each summing coefficient.  The resistor's values will encode the NN coeficients.

With fixed resistors (fixed NN coefficients and hardwired architecture) such a NN will have a fixed functionality, but hey, would be fun to make an "analog OCR" (Optical Character Recognition) entirely in hardware, out of a bunch of 4000 CMOS chips and a bag of resistors. 

[tggzzz]

For reference, I've breadboarded amplifiers and switching circuits using 2N3904s and friends (fT ~ 300MHz) before.  Which go almost as fast, and at comparable bias currents (10mA).  Oscillation isn't at all guaranteed there, either, but keep in mind that might be a single transistor, or few at a time, not an array of six pairs.

My latest Philips scope, with a risetime of 200ps, has mainly BC107s in the signal path. There are three transistors with an fT of 2GHz, in the trigger circuit.

Strange, wonderful scope, with controls and measurement artefacts that would confuse most engineers. Basically you are required to visualise the signal you are trying to observe before you can fully observe it. Not a bad discipline

In contrast, I once breadboarded a Z80-CPU and a handful of other things, and that, just running at 4MHz (yes yes, implied edge rate some times higher, but it's "only" NMOS, fairly weak drive strength; the TTL bus latches (output ports for blinkenlites) were probably the worst offenders; also being that one had an LED display matrix on ribbon cable hanging off it, heh.  It worked fine for the most part, but would crash randomly -- or not really "random", but also "perfectly" randomly, in that it was reliable/consistent (weeks of uptime blinking out a set pattern) in an earlier version, but a later version I added an LFSR noise generator, after which it might run a day or a week between crashes.  (And it would crash-crash, because it was the NMOS CPU; clock bounces or stops momentarily or whatever it was reading that upset it, and that's it, it's toast, internal state is lost, reset required.  Well maybe CMOS would crash too, I don't know, if it were a fast double-tap, that could corrupt it just as well.  But those are my assumptions anyway.  No way to tell, and actual cause doesn't matter anyway; obviously it's a marginal signal quality issue caused by the breadboard.)

The pattern sensitive intermittent operation is the worst case, of course. It is bad enough for an experienced engineer to sort it out; a beginner won't have a clue where to begin: is it software, digital, flaky connection. (Intel's first DRAM, the 1kbit 1103, had a reputation for being pattern sensitive. Oops)

My first computer was a 6800 with 128bytes of RAM on several home-made circuit boards, tested using a voltmeter, LEDs and switches. The clock input was non-TTL with strict voltage limits, so before inserting the precious 6800, I looked at it using the university's scope. That taught me about lead length and inductance Terrible construction, but I learned a lot - and that was useful when chatting with engineers during job interviews.

The worst of both worlds, however, was one time I tried breadboarding a -- I think it might've been a type-T flip-flop in ECL/CML?  That most definitely did NOT work: too many transistors, too much gain, it oscillated between stages -- at some 100MHz or so, which is a frequency consistent with lead lengths / propagation delays along such a chain, and node capacitances and all that.  (I eventually later built a variant of that circuit Manhattan-style, which worked beautifully.  It's a rather pleasing circuit, in terms of topology and construction, and might make a good project to investigate and build, if I might so humbly suggest. )

That's an example of why I push beginners away from solderless breadboards and towards better breadboard techniques such as manhattan or deadbug. Those that persist in using solderless breadboards soon find out that manhattan/deadbug is faster. Plus you have to learn which end of a soldering iron is hot

Yet another example, of more direct application / reference here, was one time where I had a ATMEGA32 breadboarded, and wired to an analog (ADC/DAC) board I had put together -- this on ground plane, hand carved / Manhattan style, with SPI leads going back to the breadboard.  Well, those fly leads were a good 10" or so long, and, you guessed it, the data was crap.  Put a ferrite bead on SCK and SDI/O, added a couple more ground wires -- no problem, solid data, reliable readings.  (Which was at a time when I "knew what I was doing", so the problem was easily recognized, verified (there was significant ringing on the signals) and addressed.)  ATMEGA isn't particularly fast (it's 5V CMOS, roughly 74HC scale I think?), but I just wasn't sure if it was fast enough to be a problem here, and it turns out it was -- good to know.

So, the stability, the coupling and risk of oscillation, the general noise levels, all of it gets worse with scale.  Telling someone they can't do a single-gate oscillator or amplifier this way?  Come on, that's BS and y'all know it.  It needs to be done carefully, and let's say might be a good learning opportunity in seeing how wire length matters -- as long as one is aware of the effect, and has the commitment to play around enough to tell -- it does take some effort to replug the circuit, making sure unused gates are tied off, supplies are wired short and well bypassed, signal lines are short and low, etc.  Conversely, if you're not interested in that kind of exploration -- maybe keep it to simpler things, like single transistors, and low bias currents where they don't sing, or add a ferrite bead around the base lead to kill any possibility of it trying.

Agreed.

But the key point is that a beginner simply won't be able to do it "carefully". Hopefully beginners won't be put off by unexplained behaviour and change to something easier such as web front ends

[Infraviolet]

To be clear, I've already made this 3MHz circuit work using both 2N3904s on a breadboard and 2N3904s (SOT23 version) on a PCB, it works well. But I'm investigating using CMOS gates for amplification this way because they let one work with a much lower count of passives, which when one has a lot of separate channels to amplify signals on gives substantial area savings on a PCB, which is pretty useful when the final design of the PCB is going to be used within projects with moving parts and therefore spatial constraints on board size. I'm also expecting that while CMOS won't let me amplify linearly* all the way rail-to-rail, it will let my signals get a bit bigger than with transistors, which will improve the accuracy of the final readouts taken at the end of the amplification and processing stages. And as the CMOS amplification circuit has a natural negative feedback to it I expect it shouldn't have the same potential for performance variation with temperature and randomly scattered device characteristsics(as Hfe is for transistors) that transistors can. I'm already expecting this CMOS version to be more current-hungry than the transistor version is, but it seems worth it for smaller board area and potentially a slightly better accuracy from having a somewhat bigger voltage for the amplified signal.

*The parameter which really matters here by the way is having a linear relationship between the peak amplitude of the input sine wave and the peak amplitude of the amplified one, a distortion of the wave would technically be alright so long as the positive peak height got linearly scaled. As things stand so long as I don't make the gain too high both the CMOS (in some of the tests so far, not in all tests yet, but the gain equation has made it clear how to do better on that front) and transistor versions have kept both a linear relationship between input vs output peak heights and have left the wave shape undistorted.


After breadboarding I'm going to design PCBs for this CMOS version too.

P.S. as beginners go, I'm a "beginner" in terms of having gaps in my knowledge and experience (I'd never used discrete transistors as anything except "digital" type switches and logic inverters until a few months back), but I've been breadboarding, PCB designing, soldering and debugging of projects for many years. I'm certainly not going to quit and take up web design. I defend the solderless breadboard mainly for the ability to change component values faster than one can de-solder (even removing an 0603, though easier than through-hole removal, takes time to do it carefully and not tear off the pad), and because one can completely change a circuit topology to test ideas in a way which isn't posible on a PCB unless you had an absolute f***-tonne of zero-ohm jumper resistors with which to reconfigure the layout.

[tggzzz]

To be clear, I've already made this 3MHz circuit work using both 2N3904s on a breadboard and 2N3904s (SOT23 version) on a PCB, it works well.

To be clear, no you haven't. You have made one circuit using NPN BJT transistors work, and now you are trying to make a second circuit using PMOS and NMOS transistors work.

P.S. as beginners go, I'm a "beginner" in terms of having gaps in my knowledge and experience (I'd never used discrete transistors as anything except "digital" type switches and logic inverters until a few months back), but I've been breadboarding, PCB designing, soldering and debugging of projects for many years. I'm certainly not going to quit and take up web design. I defend the solderless breadboard mainly for the ability to change component values faster than one can de-solder (even removing an 0603, though easier than through-hole removal, takes time to do it carefully and not tear off the pad), and because one can completely change a circuit topology to test ideas in a way which isn't posible on a PCB unless you had an absolute f***-tonne of zero-ohm jumper resistors with which to reconfigure the layout.

With solderless breadboards and DIP ICs you need absolute f***-tonne of zero-ohm jumper resistors inductors to re-configure it before experimenting.

The time/expense taken to layout a PCB and have it manufactured/shipped is noticeable, and worth avoiding where possible. Fortunately it is possible, without resorting to solderless breadboards.

If you are actually interested getting a circuit working soonest, you really need to look at manhattan and deadbug techniques[1]. There are good reasons why those techniques are favoured by experts - and even shipped as proof-of-principle products[2].

[1,2] see the refs in the link I mentioned earlier.

[T3sl4co1l]

(hmm, could use bottom text, not sure what)

[MK14]

N.B. I rewrote your post, for you.

I hate breadboards!

Then, how come, an electronics engineer, who works (or use to), for Tektronix, designing their oscilloscopes (or so I gather/think).  Seems to use them (breadboards):

See here:

[tggzzz]

Breadboards can be fine, and can be similar to using PCBs. Solderless breadboards are problematic

[nfmax]

Shahriar of The Signal Path made an excellent video tutorial (with the assistance of his brother) on exactly this topic - how to understand and analyse the 'CMOS inverter amplifier':

[tggzzz]

N.B. I rewrote your post, for you.

I hate breadboards!

Strawman argument!

I don't hate breadboards; indeed I use them fairly regularly.

So do people that are widely acknowledged to be experts, e.g.:

• Jim Williams' famous LT AN47 “High Speed Amplifier Techniques” http://cds.linear.com/docs/en/application-note/an47fa.pdf especially the tutorial section p26-31.
  
• Or this low noise example is a professional example from Jim Williams’ classic Linear Tech AppNote120 “1ppm Settling Time Measurement for a Monolithic 18-Bit DAC. When Does the Last Angel Stop Dancing on a Speeding Pinhead?”
  
  
• Or this from someone mentioned several times by name in TAoE, showing judicious use of a range of techniques in something he shipped/showed to a customer:
  
  

I do freely and willingly acknowledge that I hate solderless breadboards. And you'll note none of those experts are using solderless breadboards.

Then, how come, an electronics engineer, who works (or use to), for Tektronix, designing their oscilloscopes (or so I gather/think).  Seems to use them (breadboards):

Ah. That's no better than arguing "I walked into a road without looking, and wasn't knocked down", therefore anybody can successfully walk into any road.

[langwadt]

I recognize that board. John Larkin who post on sci.electronics.design made it, he gets blank ENIG boards make for such protos, never tanish and looks pretty