How to measure the pulse duration shorter than the system clock?

[Zhou Quan]

Thank you for clicking on this question! My description of the problem may not be very clear. I will express it in as much detail as possible.
I'm a beginner of ZYNQ. Recently, I'm trying to design a high-resolution Frequency Counter by using Red Pitaya(a Zynq 7020 SoC kit). At the beginning, I used the "reciprocal counting method". Its accuracy depends on the system clock. Since the start trigger and close trigger of the counting gate are not completely aligned with the rising edge of the system clock.  In general it can be ignored. However, when I want to further improve the resolution,  It is necessary to measure the "gap time "between these triggers and the following clock pulse.
So far, I have come up with two solutions:
1. Connect an external capacitor charging circuit. It will charge the capacitor when start trigger arrives, and stop charging  when the following clock pulse arrives. In this way we transfer the "gap time" into the voltage. Then we can read out the voltage by ADC and calculate the time. The problem is the behavior of ADC may influence the capacitor.
2. Connect an external circuit to scaling the time interval. This idea comes from the other's project: https://www.eevblog.com/forum/projects/diy-interpolating-frequency-counter-fc-510/. In the schematics, I noticed an external analog circuit(shown below). According to the simulation results, I guess its function is to extend this short gap time, so we can use the clock signal to measure it. At last. we will scale down the measurement results. However, I can't understand the principle of this circuit.
These are my questions and attempts. I would appreciate it if anyone can give me some help and suggestions!

[alexanderbrevig]

Did you hear the latest AmpHour? What you are talking about reminded me about it https://theamphour.com/579-adc-chip-design-with-anthony-wall/

[Marco]

A pulse stretcher is an extension of a time to voltage converter. The time to voltage converter can be directly measured with an ADC, the pulse stretcher converts the voltage back to a pulse which can be measured with a counter. With a high resolution ADC available it makes more sense to just use a time to voltage conversion circuit.

The circuit you posted charges the capacitor with ~10 mA during the pulse and then discharges it with ~100 uA afterwards, together with the logic level switching in the CPLD is a rudimentary pulse stretcher.

[Zhou Quan]

Many Thanks, Marco! You are the first person who refers to the word "pulse stretcher". That's exactly what I need! I googled pulse stretcher and I think I've got a rough idea of how Pulse Stretcher works. Unfortunately, I'm still a little confused about the posted circuit. I try to simulate its behavior by LT Spice. I used a PULSE voltage source to generate a single short pulse(3V height, 40ns width) at the input. However, The output pulse is not stretched as expected, but becomes a smooth line. Could you help me to figure it out?
Thanks!

[Zhou Quan]

Thanks for your reply! I'm afraid I don't understand that page. Is it a product leaflet?

[dietert1]

There are two time constamts. While charging during the short input pulse it is R12 times C3. While discharging it is R13 times C3. The pulse stretcher has a large dead time after each input pulse, since the output pulse is about 80 times longer. So after each 50 nsec input pulse it will take about 4 usec or more to measure the output pulse.

Regards, Dieter

[Zhou Quan]

Dear Dieter, Thanks for your reply! Does the "dead time" mean I should wait 5ns or longer to see the stretched pulse?
I just tried to extend the stop time, the 'Pulseout' result, however, seems to be a constant round 2.3V. It only fluctuates very slightly at the rising and falling edges of the input pulse. Did I make some mistakes in simulation?

 

[dietert1]

Dead time is the minimum delay between two input pulses. Should be about 10 usec in the example. If another pulse follows during the deadtime, the circuit won't work as intended.

Regards, Dieter

[RoGeorge]

See if this method suits your application:
https://www.eevblog.com/forum/fpga/ebaz4205-(zynq-7000-based-development-board)/msg3382490/#msg3382490

[Cerebus]

There are two time constamts. While charging during the short input pulse it is R12 times C3. While discharging it is R13 times C3. The pulse stretcher has a large dead time after each input pulse, since the output pulse is about 80 times longer. So after each 50 nsec input pulse it will take about 4 usec or more to measure the output pulse.

Regards, Dieter

Not sure where you're getting that from, R12 is part of a bias divider chain. Did you mean R9, annotated with the rather odd K12 rather than 0k12 or even 120R?

Anyway, for Zhou Quan's benefit, a quick explanation of how this works:



The divider chain formed by R10, R11 and R12 provides bias voltages of 3V to the base of VT4 and 1.7V to the base of VT5. VT5 in combination with the base bias and the 10k emitter resistor forms a constant current sink of about 100uA. VT3 and VT4 form a classic long-tailed differential pair, here being used as a current switch. The bias of 3V on VT4 sets the point at which this switched from one side to the other.

When the input, at R7 is low - VT3 is switched on, VT4 switched off and all the current from R9 is directed to earth via VT3. Meantime, VT5 acting as a current sink is discharging C3. The final voltage C3 settles to is difficult to be precise about without simulating it, but it's probably going to be about 1.2V to 1.3V.

Now, when a pulse happens the input goes high and VT3 switches off,  VT4 switches on and R9 is going to act as a [rather poor] constant current source. The emitter of VT3 is going to rise to about 3.9V, so the voltage across R9 will be 1.1V and so it will source about 9.2mA. This 9.2mA will charge C3 via VT4 (All the time this is happening VT5 is still sinking ~100uA and slightly reducing the charging rate of C3). The voltage on C3 will rise roughly linearly at about 9.1V/us.

When the pulse stops the transistors will revert to their previous configuration. At this instant the voltage on C3 will be proportional to the pulse width plus its initial voltage. VT4 will stop providing charging current and the constant current sink formed by VT5 will now start to discharge the capacitor until it reaches its quiescent 1.2V to 1.3V. The time it takes to do so will be proportional to the input pulse width times the ratio of the net charging current (9.1mA) to the discharge current (0.1mA) or approximately 90 times longer than the input pulse.

Quan, try your simulation again with a 3.3V pulse. With the threshold being set at the base of VT4 being 3V you're probably just not raising the base of VT3 quite high enough to turn off VT3 reliably. Make your simulation time long enough to account for the pulse stretching.

Possible problems with this circuit:

It probably has poor linearity and temperature coefficient, I'd prefer to see the bias voltages set by diode wired transistors, and a proper transistor current source instead of R9.

There may be a delay getting VT3 and VT4 out of saturation (if they get there), Schottky clamps between base and collector may help with this.

Certainly the linearity will be terrible for short pulses, better to feed it a pulse not between your asynchronous trigger and the next clock edge but the clock edge after that, adding a constant 1 clock time to the pulses fed to it to give it a decent sized minimum pulse to stretch.

The extremes of the compliance range of the pair VT4 and VT5 are only ~1.2V to ~3.5V (a range of 2.3V at most), which will limit the length of the maximum pulse you can feed into it (abs. max ~250ns) , and you will run into non-linearity before you hit the upper compliance limit, limiting the pulse length further (realistically perhaps 200ns) - this may or may not be a problem depending on your exact timings.

To deal with the drift that this is going to experience you'll need to calibrate it on the fly by feeding it a couple of pulses of known width (e.g. 1 clock time and 2 clock times) at regular intervals.

The thresholds that the capacitor voltage are going to be measured at are going to be highly dependent on what kind of input they are measured by. If you rely on a logic input as this current version of the circuit appears to expect that to add a lot of drift. Ditto the load presented by the measurement input may be highly nonlinear and further dent the circuits linearity.

Edit: It's late, somebidy should probably check my numbers. 

[Cerebus]

If anybody wants to play with it, here's one I made earlier. Opposite polarity transistors and input pulse, and a slightly different topology with a common base amplifier acting as a diode clamp and buffer on the integrator capacitor which is placed between the two arms of the current switch. Definitely a "work in progress", but it does work in simulation.

The misnamed "Spice Error Log" will show you the results of the measurement directives.

[dietert1]

cerebus, in my reply to Zhou Quan i used the part numbers of his simulation. That's fairly easy to understand. No need to create more confusion.

Regards, Dieter

[Cerebus]

cerebus, in my reply to Zhou Quan i used the part numbers of his simulation. That's fairly easy to understand. No need to create more confusion.

Regards, Dieter

The part numbers are the same for both the simulation and the original schematic. I'm try to clarify, not create confusion.

There are two time constamts. While charging during the short input pulse it is R12 times C3. While discharging it is R13 times C3.

Surely you meant to say R9 and R13?