how would you connect these power planes

[hsn93]

hello,

how would you connect these planes which are close to each other

VDDIO - 3v3
VDDCORE 1v2



having 4 layers pcb .. (should i consider 6?)
is it ok to have the 3v3 plane on layer 2 , and 1v2 on layer 3 ? or i should put a ground plane in between them ??
like this:

i try my best to put all component in the top layer as well.

suggestions?

[hsn93]

hello, i though this is to generic question and thats why nobody answered.

for me i asked because i dont know what is good way to approach this,


so i will put another picture with a specific question:


shown in the picture 3 planes in (top plane red = gnd) - 2nd layer brown (3v3) - 3rd layer cyan (1v2)
not shown (bottom layer blue = gnd)

there is highlighted net which i can route in any layer. i remember that i watch videos of dave "or fedevel academy" saying its good practice to route in one layer as much as possible .. the thing is that this will cut the ground
"long trace = cut the plane"

now what would be the best practice

to route in top layer and place vias between top and bottom ground planes like this?


or to change the layers of the net like this:

[hsn93]

hello, there was no reply on this post so i thought its so stupid question or to general. hence i went through the design and i want to ask more specific question,


here is a video showing RF injection to crystal oscillator.

so a question about the planes:

is it good idea to not put a power plane under the crystal ? so only bottom layer (ground plane)?

here is a picture of what i mean:


would it have better accuracy?
i know that a oscillation tracks should not pass over tracks so would power plane consider as track ? (because current takes shortest path and the shortest path could be under the crystal at some point? so is it wise to make what i did in this picture ? refereing to XC2

[Karlo_Moharic]

put a ground plane between each power plane

[dmills]

If you are forced to use 4 layer for a two power plane design then that is about as good as you can do, but depending on what you need to fan that qfp out (And hence what happens to the ground pour) I would tend to be more concerned by the nets crossing reference plane edges then the polygons themselves.

For this reason I tend to favour a solid ground on L2 rather then the bottom layer even if it makes the power a rather complex pair of interlocking polygons on L3 & 4, then do most of the fanout on L1. This keeps the fanout above a solid ground, which is very much what you want.

It does of course compromise the reference plane for the back of the board, but 4 layers, what can you do?
Do watch the copper distribution, the layers should be reasonably symmetric to avoid the board warping.

6 layers of course is nice, but it adds reasonably significant cost.

Regards, Dan.

[T3sl4co1l]

Why not cover the whole board with inner planes?

Planes must only be cut where a different common mode AC voltage is required.  If everything is common ground in your circuit, pour ground over the whole thing.  Done.

VCC might not be needed over the whole board, in which case you can cut it up and put other supplies in where needed.  Bigger and wider is better.  No need to hide and "save copper", it's better with more.

Avoid routing traces on inner layers if at all possible.  Every trace on those layers creates a hole in the plane, making it worse.

I rarely use outer layer (top/bottom) pours on 4-layer boards because it's a pain to stitch them together with vias around every gap.

There is almost no reason to pour a routing layer without stitching; if you don't have the space or time to stitch it, you might as well leave it off.

Tim

[hsn93]

hello, thanks for your reply, this is the board:

If you are forced to use 4 layer for a two power plane design then that is about as good as you can do, but depending on what you need to fan that qfp out (And hence what happens to the ground pour) I would tend to be more concerned by the nets crossing reference plane edges then the polygons themselves.

reference plane edges = ground plane edges?

For this reason I tend to favour a solid ground on L2 rather then the bottom layer even if it makes the power a rather complex pair of interlocking polygons on L3 & 4, then do most of the fanout on L1. This keeps the fanout above a solid ground, which is very much what you want.

so a solid ground on layer 2,
layer 1 = nets and tracks,
what if you need to pass them to other layer, you pass them to layer 3?
where would you put 3v3 plane and 1v2 plane ? L3 & L4 ?
this means all your ground pins of the MCU should pass through via to the ground plane? is it good?

Do watch the copper distribution, the layers should be reasonably symmetric to avoid the board warping.

hmm i looked on the internet for this, do you mean the oz and copper weight of L1 & L2 = L3 & L4 ? or i should even care not to put planes on left side of the board and not fill the right side?

[dmills]

Reference plane = whatever plane is directly adjacent to a signal line, usually you try to make this ground, but it can be a power plane.

The trick is to avoid having a signal with a fast edge (it does not matter what the frequency is, only the rise and fall times) cross the edge of its reference plane as that will cause the return current (which flows in the reference plane) to have to find an alternative route causing you EMC and possibly SI problems. 

For this reason I like a single ground plane on L2 with the bulk of the fast routing on L1, the proximity of the ground plane helps in all sorts of ways even if you are not doing controlled impedance design.

I figure I could probably get both your power polygons on L4, with a buried signal layer on L3 (the other side of the ground plane) for those annoying bits of net that need to cross tracks on L1.

Vias down to the ground plane are entirely normal, they add about 1nH of inductance, not usually a big deal.

I would probably pour a ground polygon on L3 after routing the rest of the board so as to equalise the copper load with the ground plane on L2, but for a mere 4 layer board at 1.6mm it is probably not critical.

Do add stitching between the grounds if you have them on more then one layer, it nearly never hurts. 

Regards, Dan.

[hsn93]

Why not cover the whole board with inner planes?

Planes must only be cut where a different common mode AC voltage is required.  If everything is common ground in your circuit, pour ground over the whole thing.  Done.

VCC might not be needed over the whole board, in which case you can cut it up and put other supplies in where needed.  Bigger and wider is better.  No need to hide and "save copper", it's better with more.

Avoid routing traces on inner layers if at all possible.  Every trace on those layers creates a hole in the plane, making it worse.

I rarely use outer layer (top/bottom) pours on 4-layer boards because it's a pain to stitch them together with vias around every gap.

There is almost no reason to pour a routing layer without stitching; if you don't have the space or time to stitch it, you might as well leave it off.

Tim

hello, tim thank you for the reply,

Why not cover the whole board with inner planes?

so i should cover the remaining of ground on L2 and L3? (1)

Planes must only be cut where a different common mode AC voltage is required.

to be honest i didnt understand, do you mean "chassis ground = earth" ?

Avoid routing traces on inner layers if at all possible.  Every trace on those layers creates a hole in the plane, making it worse.

but even if i routed from top to bottom layer, it will make hole right? or you mean it trace cut the ground plane?

VCC might not be needed over the whole board, in which case you can cut it up and put other supplies in where needed.  Bigger and wider is better.  No need to hide and "save copper", it's better with more.

is it what i did? or do you mean this:
so i should cover the remaining of ground on L2 and L3? (1)

There is almost no reason to pour a routing layer without stitching; if you don't have the space or time to stitch it, you might as well leave it off.

but then you would route or your SMD parts on top layer with VIA to the ground layer?

[hsn93]

Reference plane = whatever plane is directly adjacent to a signal line, usually you try to make this ground, but it can be a power plane.

The trick is to avoid having a signal with a fast edge (it does not matter what the frequency is, only the rise and fall times) cross the edge of its reference plane as that will cause the return current (which flows in the reference plane) to have to find an alternative route causing you EMC and possibly SI problems. 

For this reason I like a single ground plane on L2 with the bulk of the fast routing on L1, the proximity of the ground plane helps in all sorts of ways even if you are not doing controlled impedance design.

I figure I could probably get both your power polygons on L4, with a buried signal layer on L3 (the other side of the ground plane) for those annoying bits of net that need to cross tracks on L1.

Vias down to the ground plane are entirely normal, they add about 1nH of inductance, not usually a big deal.

I would probably pour a ground polygon on L3 after routing the rest of the board so as to equalise the copper load with the ground plane on L2, but for a mere 4 layer board at 1.6mm it is probably not critical.

Do add stitching between the grounds if you have them on more then one layer, it nearly never hurts. 

Regards, Dan.

hello, thanks Dan this is more clear.
putting a ground under all tracks so less ground loop. this what i understand.

cross the edge of its reference plane as that will cause the return current (which flows in the reference plane) to have to find an alternative route causing you EMC and possibly SI problems. 

sorry but if refernce plane is not ground, how would the signal cause the return current to it ? do you mean that it will induce voltage because of electromagnetic?


and last question, if you pour L2 and L3 with ground. would you pour L1 with ground and stitch it later with L2 and L3? is it bad idea?