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I am looking to use a Microchip MCP3202 ADC, but it does not have a separate Vref, only a combined Vref/VDD pin. I'll be powering it with 3.3V, but the power rail will be unavoidably noisy (around 100mV pk-pk noise), so I think it's a good idea to filter the power supply.
Because I don't want to greatly lower the impedance of the power supply then an RC filter is not suitable, right? So I'm thinking what I need is an LC filter. But still I'm a bit of a noob at all this kind of analog stuff and I don't really know what I'm doing, especially the maths.
I've been tinkering around simulating a low-pass filter that has a cut-off frequency of about 50 kHz with 10 uH inductor and 1uF cap, but it also seems to self-oscillate around that frequency, amplifying the noise greater than the input. If I add 10 ohms series resistance (i.e. turning it into RLC), it's fine. Should I be adding the DCR of the inductor as 'R' to the simulation? Most 10 uH inductors in 0805 package (what I plan to use) seem to have a DCR spec of 1.15 ohms. Or should I not be too concerned about needing to add 10 ohms, as the ADC only consumes about 550 uA worst case (according to datasheet)? -
separate linear regulator may help to reduce ripple up to some ~1MHz
above 1MHz ferrite bead ,
inductor saturation current and parasitic capacitance will limit filtering effect
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I don't have any higher-voltage rails available from which to run a linear regulator. The noisy 3.3V is all I've got.
Is inductor saturation current ever going to come into play if I'm only drawing less than 1 mA? The 0805 I plan to use are rated for 15 mA. -
I just had a thought. I am buffering the inputs to the ADC with op-amps because I need to have a very high-impedance connection to what is being measured. Should I re-organise the filtered 3.3V so that it is supplying these op-amps as well as the ADCs? Otherwise, will the op-amps just be passing power supply noise into their outputs? Although, I do have RC filtering on the output of the op-amps...
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You can power the ADC from a proper shunt reference with a voltage between 3...3.1 V. The digital part of the ADC can tolerate at its input Vcc +0.6V (absolute maximum rating)
As long as the difference between the SPI interface maximum voltage and the shunt ref. minimum voltage stays within 0.3 V, it will work fine and the SPI interface clamping diodes will not conduct.
An LM4040 is a popular shunt reference available in 3 V, 0.1 %, 100ppm. A REF2030 is 0.05 % and 8ppm. -
Better way of doing this kind of thing is to create separate supplies for both analog and digital. Can be done with ferrite beads, resistors and capacitors coming of of the same supply voltage. By matching the supply voltage of both the digital and analog parts by trimming the series resistors there is little risk in exceeding maximum input voltages. The ADC works down to 2.7V and most likely the MCU you are using will also allow for some deviation of the supply voltage.
Also using multiple different value capacitors in the decoupling helps in reducing the noise. A friend of mine who is much more of an expert advised me to use parallel 100nF, 10nF and 1nF capacitors before and after the ferrite bead, and then the series resistor followed by a larger capacitor like 10uF. Then still add the 100nF decoupling capacitor advised for most IC's. See page 18 of the MCP3202 datasheet.
The different value capacitors seem to have different responses at different frequencies and therefore do a better job in filtering a wider spectrum, so I'm told. -
How much bandwidth do you need?
If not much, you might average it all out on the digital side and kinda not care. It's not a great solution, as the noise will alias and there is an asymmetry to it (it's ratiometric, in particular in the denominator, not additive), which will cause some wandering baseline that doesn't average out, but it might be small enough not to mind (i.e. consider the effect of 3.35 vs. 3.25V ref).
You generally want enough filtering (so, that means both signal and ref here) that aliasing is low enough not to mind, or in bands that can be digitally filtered post-conversion.
What spectrum is the noise? If it's switching noise, an LC filter is fine. If it's all kinds of crunchy, from various causes, erratic time constants, likely you need an LDO.
Could even spring for a switching converter, in a pinch. A bit over-the-top, but maybe not as bad as it sounds: regulating charge pumps are available for example, which could be a single-chip (give or take external caps) solution.
Note the LDO can be very thin: say 3.0V, so logic levels aren't violated. You don't want e.g. 3.6V+ beginning to forward-bias the ESD clamp diodes into a device at 3.0V supply, or 3.3 into 2.7, but 3.3 into 3.0-3.1 would be perfectly fine. Downside: LDO PSRR is typically trash to begin with, and it's even worse operating so close to dropout. Again, it's only a thing if you need low frequency filtering.
Bonus: LDO at least gives [the chance for a] more accurate supply/ref, potentially reducing calibration error.
Devil's advocate: if your input signals are ratiometric with the supply, this whole exercise is making things actually worse!
Note that, if you do use an LC filter, include sufficient ESR to keep it dampened. Probably an 0.1uF local HF bypass is all that's needed, then the rest can be lossy "bulk", say 10uF electrolytic, and 1-10uH choke, or proportionally scaled values for other cutoff frequencies.
Tim -
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Bonus: LDO at least gives [the chance for a] more accurate supply/ref, potentially reducing calibration error.
My posts suggests the use of a shunt reference instead of an LDO which is a better option if power loss is not an issue. It doesn't suffer from reduced PSSR when operating close to Vin like the LDO. -
I am looking to use a Microchip MCP3202 ADC, but it does not have a separate Vref, only a combined Vref/VDD pin. I'll be powering it with 3.3V, but the power rail will be unavoidably noisy (around 100mV pk-pk noise), so I think it's a good idea to filter the power supply.
Because I don't want to greatly lower the impedance of the power supply then an RC filter is not suitable, right? So I'm thinking what I need is an LC filter. But still I'm a bit of a noob at all this kind of analog stuff and I don't really know what I'm doing, especially the maths.
I've been tinkering around simulating a low-pass filter that has a cut-off frequency of about 50 kHz with 10 uH inductor and 1uF cap, but it also seems to self-oscillate around that frequency, amplifying the noise greater than the input. If I add 10 ohms series resistance (i.e. turning it into RLC), it's fine. Should I be adding the DCR of the inductor as 'R' to the simulation? Most 10 uH inductors in 0805 package (what I plan to use) seem to have a DCR spec of 1.15 ohms. Or should I not be too concerned about needing to add 10 ohms, as the ADC only consumes about 550 uA worst case (according to datasheet)?
Hi,
It is difficult to predict what will happen with an LC filter like that. Luckily with that 10 Ohm series resistor it is overdamped. The lowest you can go on that is around 7 Ohms maybe a little less. But if you have to use a 10 Ohm resistor, why not go with just a large capacitor in parallel with a small ceramic like 0.1uf ? That's the more typical solution. Even more typical is just the large cap in parallel with a ceramic 0.1uf cap and no resistor.
It is interesting though that even a 2uH inductor and cap filter filters out a lot of ripple when used as a post filter on a buck circuit. -
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Bonus: LDO at least gives [the chance for a] more accurate supply/ref, potentially reducing calibration error.
My posts suggests the use of a shunt reference instead of an LDO which is a better option if power loss is not an issue. It doesn't suffer from reduced PSSR when operating close to Vin like the LDO.
Are you sure about that?
Tim -
How much bandwidth do you need?
I'm only measuring voltage rails on a device-under-test to determine whether their levels are in-spec, not any kind of varying signal, so hardly any bandwidth at all.If not much, you might average it all out on the digital side and kinda not care. It's not a great solution, as the noise will alias and there is an asymmetry to it (it's ratiometric, in particular in the denominator, not additive), which will cause some wandering baseline that doesn't average out, but it might be small enough not to mind (i.e. consider the effect of 3.35 vs. 3.25V ref).
I might do some averaging on the digital side, not sure yet. Although, I want to ensure the voltage rails under test aren't fluctuating so averaging over too much of a period will probably mask what I'm trying to measure. What I'm probably going to be looking at is not only the mean value of samples but also their std. deviation too.What spectrum is the noise? If it's switching noise, an LC filter is fine. If it's all kinds of crunchy, from various causes, erratic time constants, likely you need an LDO.
I think it's switching noise from a DC-DC converter mainly. No idea what frequency the switcher is running at. I should probably try and analyse it in more detail than I've done so far: that is, poke it briefly with the 'scope and go "ew, that's dirtier than I was expecting".
Note the LDO can be very thin: say 3.0V, so logic levels aren't violated. You don't want e.g. 3.6V+ beginning to forward-bias the ESD clamp diodes into a device at 3.0V supply, or 3.3 into 2.7, but 3.3 into 3.0-3.1 would be perfectly fine. Downside: LDO PSRR is typically trash to begin with, and it's even worse operating so close to dropout. Again, it's only a thing if you need low frequency filtering.
Bonus: LDO at least gives [the chance for a] more accurate supply/ref, potentially reducing calibration error.
I suppose an additional benefit of running the ADC and op-amps from a 3V supply is that I'll also get slightly higher resolution, as the input will be larger relative to the reference. But that's minor, and I don't particularly need super accuracy - even this 12-bit ADC is a bit overkill for my application.
I wouldn't know how to pick an LDO regulator with good PSRR, though. It seems difficult to make comparisons because the manufacturers all give specs according to different conditions. Some give it at 1kHz, some at 100kHz, etc. I'm not even sure what magnitude of PSRR is good. Is 50 dB good or poor? 70 dB? 90 dB?
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An LM4040 shunt reference maintains a dynamic resistance below 0.25 mOhm with a bias current of 1 mA up to about 350 Hz. With a 270 R bias resistor this equates into a 60 dB PSSR. Below 200 Hz the dynamic impedance is even lower and close to 100 mOhm or about 68 dB PSSR.
Does it outperform an LDO? When bypassed with a 10 µF ceramic capacitor is does for freq. above 1...10 K. But some LDO's are better than others. Some modern ones are very good while some are just bad. The REF2030 I mentioned earlier is a series reference. (My mistake) When it comes to high frequency noise, the LM4040 when bypassed with 10 µF outperforms the REF2030 for freq. above 1 K.
Besides, at low currents, the PSSR plot might still be valid because the LDO is not operating close to or in saturation. But the way they specify drop out can be tricky. I usually calculate the MOSFET on resistance. That seems a more valid approach to me. But that only works for LDO's with output voltages > 2.5 V.
A shunt ref with a very low dynamic resistance is the AZ431L. 50 mOhm from DC up to almost 50 KHz. This would translate onto 75 dB PSSR from DC up to 50 K without a bypass capacitor. Not bad.
But your question is valid because this turns out to be an edge case.QuoteI wouldn't know how to pick an LDO regulator with good PSRR, though. It seems difficult to make comparisons because the manufacturers all give specs according to different conditions. Some give it at 1kHz, some at 100kHz, etc. I'm not even sure what magnitude of PSRR is good. Is 50 dB good or poor? 70 dB? 90 dB?
The first question to answer is how many bits you need.
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I think it's switching noise from a DC-DC converter mainly. No idea what frequency the switcher is running at. I should probably try and analyse it in more detail than I've done so far: that is, poke it briefly with the 'scope and go "ew, that's dirtier than I was expecting".
Yeah, do that. Then figure how much LC is needed, and if an LDO is still needed to cover the bottom end / save space.QuoteI wouldn't know how to pick an LDO regulator with good PSRR, though. It seems difficult to make comparisons because the manufacturers all give specs according to different conditions. Some give it at 1kHz, some at 100kHz, etc. I'm not even sure what magnitude of PSRR is good. Is 50 dB good or poor? 70 dB? 90 dB?
Oh well they usually give it at DC. So you get numbers in the table like 60, 80, 100dB that are meaningless. But you pop over to the PSRR vs. freq plot (if they give it, and if not, keep shopping!) and see what it's like. Note that it usually falls near zero at high frequencies (control loop GBW, i.e. feedback gain drops below 1 around that point -- it literally can't respond anymore), at which point bypass caps take over, there might be peaks or valleys, it goes back up at HF... this all depends on the fixture used (which they never tell you about), things like stray L in the layout, ESL of the caps, how many caps are used and in what combination (parallel (ceramic) caps have resonance between them), but in any case you can do the same, your LC filter will take over above cutoff (and preferably somewhat below, as needed).
But note that PSRR vs. F is usually done at some large-ish drop, maybe 1V or more. If they give a series of curves with Vdrop as parameter, that's great. Assume it gets worse as Vdrop goes down.
Doing statistics, will be sensitive to AC readings, and you'll want a stable reading to tell more from less. If it's unstable to begin with, at least seeing the variance increase would be a thing, but you can't tell if it's in/out of phase with the system noise floor (which isn't noise at all but coherent: peaks in the frequency spectrum), and any time those correlate, you end up with (constructive/destructive) interference, and you could see the variance decrease instead, which would just be strange, but is perfectly reasonable when things line up just right.
Note that, so far, you've implied these signals are independent, or can be assumed as such. You might know better. If the other supplies are derived from the first, then that ripple carries through according to the transfer functions of everything between, and the statistics will be stable. If they're separate switching circuits, likely not, but there could still be weird ratios and mixing tones that result in fluctuating readings. Gathering statistics over a long enough period, reduces those fluctuations to only when beat frequencies are on the order of that collection period, making such error much rarer, and if the frequencies themselves aren't that stable in the first place (e.g. COT controllers, spread spectrum), the error can also be made small.
Tim -
I measured the noise on the 3.3V power. It turns out what I saw previously was actually intermittent noise. (Either that or I was looking at baseline but was zoomed in and mis-read the V/div setting.
) The baseline noise is about 17 mV pk-pk, so not that bad. But the intermittent noise - the source of which I'm not sure of - is about 45 mV pk-pk, and appears to be of mixed frequency.
Here's a couple of examples of the baseline noise level, and the intermittent noise.
While the former is probably I feel on the verge of tolerable as a Vref for my ADC application - I probably only need to measure the inputs with perhaps ±10 mV - the latter is what I definitely want to filter out. Is an LC filter going to help me here?
I've also been looking at low-noise, high-PSRR linear regulators. I found the TI TPS7A20 and the LP5907. Do they look reasonable? The former seems to be slightly better PSRR-wise at low-loads, although the latter has much lower drop-out voltage.Note that it usually falls near zero at high frequencies (control loop GBW, i.e. feedback gain drops below 1 around that point -- it literally can't respond anymore), at which point bypass caps take over, there might be peaks or valleys, it goes back up at HF... this all depends on the fixture used (which they never tell you about), things like stray L in the layout, ESL of the caps, how many caps are used and in what combination (parallel (ceramic) caps have resonance between them), but in any case you can do the same, your LC filter will take over above cutoff (and preferably somewhat below, as needed).
Ah, so you think I should combine both approaches - a high-PSRR LDO and an LC filter? I can see how that might be better. The LC filter handles all the high-frequency stuff, and the LDO handles the lower-frequency stuff within it's peak range for PSRR. Hmm, perhaps I shall consider that...
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For the intermittent noise it might well be that your probe is picking that up. That is always a problem with using an oscilloscope, is the signal you see actually there, or is it there because you are probing the circuit. For more precise measurement it is important to have as little unshielded wire probing the circuit and have the ground connected as close by as possible, not using the long ground lead.
This is where the springs that can be connected to the end of the clip less probe comes in. You have the probe tip and a ground ring there. It is not easy to probe this way, but it does reduce on false readings. -
This is where the springs that can be connected to the end of the clip less probe comes in. You have the probe tip and a ground ring there. It is not easy to probe this way, but it does reduce on false readings.
Yeah, I wanted to use the spring clip, but power and ground were too far apart - on a connector but not adjacent to each other.
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Would like to see a zoom of the intermittent stuff; it looks high frequency still, just with a lower repeat rate. Switching junk perhaps. You can also see after an LC filter, which also if the output still shows anomalously high high-frequency content, will give further clues as to whether it's CM error or real DM signal you're measuring. You can also probe ground to see ground-loop voltage/current.
Tim