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FPGA / Re: Reverse engineering Anlogic AL3_10 FPGA
« Last post by pcprogrammer on Today at 05:33:37 pm »Hi Atlan,
I looked at what you changed and the reduction of the clock divider widths should not make a difference in the working and only reduce the number of logic cells used.
The other change, where you invert the adc1_encA and adc2_encA signals should also not make a difference to what the original code did.
Keep in mind that in HDL actions are taken in parallel in this case. So with the code as it was the two encA registers are set to what the encB registers were before the clock pulse and the encB registers are inverted on the clock pulse. In simulation it works as intended.
With your setup it inverts all four of the signals instead of copying. Internally it most likely is just a difference in the routing.
I have not tested it on the scope as it will do just the same as what I tested 2 years ago.
Also be aware that the original design is as crap as can be. There can be clock domain crossing and meta stability issues with it. If your intent is to improve things, my advice is to start over and make your own design.
Some useful threads might be:
https://www.eevblog.com/forum/fpga/beginner-questions/msg4646935/#msg4646935
https://www.eevblog.com/forum/fpga/what-is-a-beter-write-enable/msg4074163/#msg4074163
https://www.eevblog.com/forum/fpga/why-does-this-dds-code-fail/msg4066636/#msg4066636
BrianHG is very good and helped me quite a bit.
Or take a look at the projects on fpga4fun:
https://www.fpga4fun.com/digitalscope.html
I looked at what you changed and the reduction of the clock divider widths should not make a difference in the working and only reduce the number of logic cells used.
The other change, where you invert the adc1_encA and adc2_encA signals should also not make a difference to what the original code did.
Keep in mind that in HDL actions are taken in parallel in this case. So with the code as it was the two encA registers are set to what the encB registers were before the clock pulse and the encB registers are inverted on the clock pulse. In simulation it works as intended.
With your setup it inverts all four of the signals instead of copying. Internally it most likely is just a difference in the routing.
I have not tested it on the scope as it will do just the same as what I tested 2 years ago.
Also be aware that the original design is as crap as can be. There can be clock domain crossing and meta stability issues with it. If your intent is to improve things, my advice is to start over and make your own design.
Some useful threads might be:
https://www.eevblog.com/forum/fpga/beginner-questions/msg4646935/#msg4646935
https://www.eevblog.com/forum/fpga/what-is-a-beter-write-enable/msg4074163/#msg4074163
https://www.eevblog.com/forum/fpga/why-does-this-dds-code-fail/msg4066636/#msg4066636
BrianHG is very good and helped me quite a bit.
Or take a look at the projects on fpga4fun:
https://www.fpga4fun.com/digitalscope.html