Simulation and testbenching is absolutely essential for big projects. The idea is you isolate your design into functional modules and write a spec for its I/O, then design a verilog testbench that makes sure it performs as designed by generating stimuli and checking the output.
Compile for simulation takes seconds to minutes. A fulll synthesis/P&R on real hardware takes minutes to hours. Iteration is more easily done via simulation.
That said, there are some things you can't simulate, and I've done a lot without it.
As an example: say you're writing a SDRAM controller, which is a pretty basic thing, but can also be difficult to ensure you don't violate any of the various timing specs. The SDRAM has no way of telling you you are violating its timing, except that it may fail 2 years down the road in a hot place on a certain phase of the moon. So you download Micron's behavioral model and wire it up to your controller as if it were real memory. Then it can print out debug messages about things the chip wouldn't like if you were actually controlling it.